mirror of https://gitee.com/openkylin/qemu.git
target-mips: add msa_reset(), global msa register
add msa_reset() and global msa register (d type only) Reviewed-by: James Hogan <james.hogan@imgtec.com> Signed-off-by: Yongbok Kim <yongbok.kim@imgtec.com> Signed-off-by: Leon Alrae <leon.alrae@imgtec.com>
This commit is contained in:
Yongbok Kim
Leon Alrae
parent
239dfebe12
commit
863f264d10
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@ -1356,6 +1356,7 @@ static TCGv cpu_dspctrl, btarget, bcond;
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static TCGv_i32 hflags;
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static TCGv_i32 fpu_fcr0, fpu_fcr31;
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static TCGv_i64 fpu_f64[32];
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static TCGv_i64 msa_wr_d[64];
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static uint32_t gen_opc_hflags[OPC_BUF_SIZE];
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static target_ulong gen_opc_btarget[OPC_BUF_SIZE];
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@ -1454,6 +1455,25 @@ static const char * const fregnames[] = {
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"f24", "f25", "f26", "f27", "f28", "f29", "f30", "f31",
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};
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static const char * const msaregnames[] = {
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"w0.d0", "w0.d1", "w1.d0", "w1.d1",
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"w2.d0", "w2.d1", "w3.d0", "w3.d1",
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"w4.d0", "w4.d1", "w5.d0", "w5.d1",
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"w6.d0", "w6.d1", "w7.d0", "w7.d1",
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"w8.d0", "w8.d1", "w9.d0", "w9.d1",
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"w10.d0", "w10.d1", "w11.d0", "w11.d1",
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"w12.d0", "w12.d1", "w13.d0", "w13.d1",
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"w14.d0", "w14.d1", "w15.d0", "w15.d1",
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"w16.d0", "w16.d1", "w17.d0", "w17.d1",
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"w18.d0", "w18.d1", "w19.d0", "w19.d1",
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"w20.d0", "w20.d1", "w21.d0", "w21.d1",
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"w22.d0", "w22.d1", "w23.d0", "w23.d1",
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"w24.d0", "w24.d1", "w25.d0", "w25.d1",
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"w26.d0", "w26.d1", "w27.d0", "w27.d1",
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"w28.d0", "w28.d1", "w29.d0", "w29.d1",
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"w30.d0", "w30.d1", "w31.d0", "w31.d1",
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};
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#define MIPS_DEBUG(fmt, ...) \
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do { \
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if (MIPS_DEBUG_DISAS) { \
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@ -17206,6 +17226,27 @@ static void decode_opc_special3(CPUMIPSState *env, DisasContext *ctx)
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}
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}
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/* MIPS SIMD Architecture (MSA) */
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static inline int check_msa_access(DisasContext *ctx)
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{
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if (unlikely((ctx->hflags & MIPS_HFLAG_FPU) &&
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!(ctx->hflags & MIPS_HFLAG_F64))) {
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generate_exception(ctx, EXCP_RI);
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return 0;
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}
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if (unlikely(!(ctx->hflags & MIPS_HFLAG_MSA))) {
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if (ctx->insn_flags & ASE_MSA) {
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generate_exception(ctx, EXCP_MSADIS);
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return 0;
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} else {
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generate_exception(ctx, EXCP_RI);
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return 0;
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}
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}
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return 1;
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}
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static void decode_opc (CPUMIPSState *env, DisasContext *ctx)
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{
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int32_t offset;
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@ -18136,6 +18177,15 @@ void mips_tcg_init(void)
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fpu_f64[i] = tcg_global_mem_new_i64(TCG_AREG0, off, fregnames[i]);
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}
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for (i = 0; i < 32; i++) {
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int off = offsetof(CPUMIPSState, active_fpu.fpr[i].wr.d[0]);
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msa_wr_d[i * 2] =
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tcg_global_mem_new_i64(TCG_AREG0, off, msaregnames[i * 2]);
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off = offsetof(CPUMIPSState, active_fpu.fpr[i].wr.d[1]);
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msa_wr_d[i * 2 + 1] =
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tcg_global_mem_new_i64(TCG_AREG0, off, msaregnames[i * 2 + 1]);
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}
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cpu_PC = tcg_global_mem_new(TCG_AREG0,
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offsetof(CPUMIPSState, active_tc.PC), "PC");
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for (i = 0; i < MIPS_DSP_ACC; i++) {
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@ -18243,6 +18293,7 @@ void cpu_state_reset(CPUMIPSState *env)
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env->CP0_PageGrain_rw_bitmask = env->cpu_model->CP0_PageGrain_rw_bitmask;
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env->CP0_PageGrain = env->cpu_model->CP0_PageGrain;
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env->active_fpu.fcr0 = env->cpu_model->CP1_fcr0;
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env->msair = env->cpu_model->MSAIR;
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env->insn_flags = env->cpu_model->insn_flags;
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#if defined(CONFIG_USER_ONLY)
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@ -18340,6 +18391,11 @@ void cpu_state_reset(CPUMIPSState *env)
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env->CP0_Status |= (1 << CP0St_FR);
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}
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/* MSA */
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if (env->CP0_Config3 & (1 << CP0C3_MSAP)) {
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msa_reset(env);
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}
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compute_hflags(env);
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cs->exception_index = EXCP_NONE;
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}
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@ -84,6 +84,7 @@ struct mips_def_t {
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int32_t CP0_TCStatus_rw_bitmask;
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int32_t CP0_SRSCtl;
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int32_t CP1_fcr0;
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int32_t MSAIR;
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int32_t SEGBITS;
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int32_t PABITS;
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int32_t CP0_SRSConf0_rw_bitmask;
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@ -729,3 +730,36 @@ static void mvp_init (CPUMIPSState *env, const mips_def_t *def)
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(0x0 << CP0MVPC1_PCX) | (0x0 << CP0MVPC1_PCP2) |
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(0x1 << CP0MVPC1_PCP1);
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}
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static void msa_reset(CPUMIPSState *env)
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{
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#ifdef CONFIG_USER_ONLY
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/* MSA access enabled */
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env->CP0_Config5 |= 1 << CP0C5_MSAEn;
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env->CP0_Status |= (1 << CP0St_CU1) | (1 << CP0St_FR);
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#endif
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/* MSA CSR:
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- non-signaling floating point exception mode off (NX bit is 0)
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- Cause, Enables, and Flags are all 0
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- round to nearest / ties to even (RM bits are 0) */
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env->active_tc.msacsr = 0;
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/* tininess detected after rounding.*/
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set_float_detect_tininess(float_tininess_after_rounding,
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&env->active_tc.msa_fp_status);
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/* clear float_status exception flags */
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set_float_exception_flags(0, &env->active_tc.msa_fp_status);
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/* set float_status rounding mode */
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set_float_rounding_mode(float_round_nearest_even,
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&env->active_tc.msa_fp_status);
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/* set float_status flush modes */
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set_flush_to_zero(0, &env->active_tc.msa_fp_status);
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set_flush_inputs_to_zero(0, &env->active_tc.msa_fp_status);
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/* clear float_status nan mode */
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set_default_nan_mode(0, &env->active_tc.msa_fp_status);
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}
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