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net: cadence_gem: Fix irq update w.r.t queue 

Set irq's specific to a queue, present implementation is setting q1 irq
based on q0 status.

Signed-off-by: Sai Pavan Boddu <sai.pavan.boddu@xilinx.com>
Reviewed-by: Edgar E. Iglesias <edgar.iglesias@xilinx.com>
Signed-off-by: Jason Wang <jasowang@redhat.com>
This commit is contained in:
Sai Pavan Boddu 2020-05-12 20:24:45 +05:30 committed by Jason Wang
parent 96ea126a8d
commit 86a29d4c72
1 changed files with 3 additions and 22 deletions
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25
hw/net/cadence_gem.c
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@ -554,29 +554,10 @@ static void gem_update_int_status(CadenceGEMState *s)
{ {
int i; int i;
if (!s->regs[GEM_ISR]) { qemu_set_irq(s->irq[0], !!s->regs[GEM_ISR]);
/* ISR isn't set, clear all the interrupts */
for (i = 0; i < s->num_priority_queues; ++i) {
qemu_set_irq(s->irq[i], 0);
}
return;
}
/* If we get here we know s->regs[GEM_ISR] is set, so we don't need to for (i = 1; i < s->num_priority_queues; ++i) {
* check it again. qemu_set_irq(s->irq[i], !!s->regs[GEM_INT_Q1_STATUS + i - 1]);
*/
if (s->num_priority_queues == 1) {
/* No priority queues, just trigger the interrupt */
DB_PRINT("asserting int.\n");
qemu_set_irq(s->irq[0], 1);
return;
}
for (i = 0; i < s->num_priority_queues; ++i) {
if (s->regs[GEM_INT_Q1_STATUS + i]) {
DB_PRINT("asserting int. (q=%d)\n", i);
qemu_set_irq(s->irq[i], 1);
}
} }
} }