mirror of https://gitee.com/openkylin/qemu.git
target-arm: A64: add support for bitfield insns
This patch implements the C3.4.2 Bitfield instructions: SBFM, BFM, UBFM. Signed-off-by: Claudio Fontana <claudio.fontana@linaro.org> Signed-off-by: Peter Maydell <peter.maydell@linaro.org> Reviewed-by: Richard Henderson <rth@twiddle.net>
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@ -698,10 +698,62 @@ static void disas_movw_imm(DisasContext *s, uint32_t insn)
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unsupported_encoding(s, insn);
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}
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/* Bitfield */
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/* C3.4.2 Bitfield
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* 31 30 29 28 23 22 21 16 15 10 9 5 4 0
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* +----+-----+-------------+---+------+------+------+------+
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* | sf | opc | 1 0 0 1 1 0 | N | immr | imms | Rn | Rd |
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* +----+-----+-------------+---+------+------+------+------+
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*/
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static void disas_bitfield(DisasContext *s, uint32_t insn)
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{
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unsupported_encoding(s, insn);
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unsigned int sf, n, opc, ri, si, rn, rd, bitsize, pos, len;
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TCGv_i64 tcg_rd, tcg_tmp;
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sf = extract32(insn, 31, 1);
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opc = extract32(insn, 29, 2);
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n = extract32(insn, 22, 1);
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ri = extract32(insn, 16, 6);
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si = extract32(insn, 10, 6);
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rn = extract32(insn, 5, 5);
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rd = extract32(insn, 0, 5);
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bitsize = sf ? 64 : 32;
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if (sf != n || ri >= bitsize || si >= bitsize || opc > 2) {
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unallocated_encoding(s);
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return;
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}
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tcg_rd = cpu_reg(s, rd);
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tcg_tmp = read_cpu_reg(s, rn, sf);
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/* OPTME: probably worth recognizing common cases of ext{8,16,32}{u,s} */
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if (opc != 1) { /* SBFM or UBFM */
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tcg_gen_movi_i64(tcg_rd, 0);
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}
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/* do the bit move operation */
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if (si >= ri) {
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/* Wd<s-r:0> = Wn<s:r> */
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tcg_gen_shri_i64(tcg_tmp, tcg_tmp, ri);
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pos = 0;
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len = (si - ri) + 1;
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} else {
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/* Wd<32+s-r,32-r> = Wn<s:0> */
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pos = bitsize - ri;
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len = si + 1;
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}
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tcg_gen_deposit_i64(tcg_rd, tcg_rd, tcg_tmp, pos, len);
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if (opc == 0) { /* SBFM - sign extend the destination field */
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tcg_gen_shli_i64(tcg_rd, tcg_rd, 64 - (pos + len));
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tcg_gen_sari_i64(tcg_rd, tcg_rd, 64 - (pos + len));
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}
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if (!sf) { /* zero extend final result */
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tcg_gen_ext32u_i64(tcg_rd, tcg_rd);
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}
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}
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/* C3.4.3 Extract
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