diff --git a/target-arm/op.c b/target-arm/op.c
index a27db0085e..7545bb0f13 100644
--- a/target-arm/op.c
+++ b/target-arm/op.c
@@ -485,6 +485,11 @@ void OPPROTO op_rorl_T1_im(void)
     T1 = ((uint32_t)T1 >> shift) | (T1 << (32 - shift));
 }
 
+void OPPROTO op_rrxl_T1(void)
+{
+    T1 = ((uint32_t)T1 >> 1) | ((uint32_t)env->CF << 31);
+}
+
 /* T1 based, set C flag */
 void OPPROTO op_shll_T1_im_cc(void)
 {
@@ -512,6 +517,14 @@ void OPPROTO op_rorl_T1_im_cc(void)
     T1 = ((uint32_t)T1 >> shift) | (T1 << (32 - shift));
 }
 
+void OPPROTO op_rrxl_T1_cc(void)
+{
+    uint32_t c;
+    c = T1 & 1;
+    T1 = ((uint32_t)T1 >> 1) | ((uint32_t)env->CF << 31);
+    env->CF = c;
+}
+
 /* T2 based */
 void OPPROTO op_shll_T2_im(void)
 {
diff --git a/target-arm/translate.c b/target-arm/translate.c
index 69bc8e224b..18caa81212 100644
--- a/target-arm/translate.c
+++ b/target-arm/translate.c
@@ -365,6 +365,11 @@ static void disas_arm_insn(DisasContext *s)
                     } else {
                         gen_shift_T1_im[shiftop](shift);
                     }
+                } else if (shiftop == 3) {
+                    if (logic_cc)
+                        gen_op_rrxl_T1_cc();
+                    else
+                        gen_op_rrxl_T1();
                 }
             } else {
                 rs = (insn >> 8) & 0xf;