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ARM shift fix (Paul Brook) 

git-svn-id: svn://svn.savannah.nongnu.org/qemu/trunk@1167 c046a42c-6fe2-441c-8c8c-71466251a162
This commit is contained in:
bellard 2004-12-08 22:28:39 +00:00
parent f7cce89882
commit 88920f344d
2 changed files with 18 additions and 0 deletions
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13
target-arm/op.c
View File

@ -485,6 +485,11 @@ void OPPROTO op_rorl_T1_im(void)
T1 = ((uint32_t)T1 >> shift) | (T1 << (32 - shift));
}
void OPPROTO op_rrxl_T1(void)
{
T1 = ((uint32_t)T1 >> 1) | ((uint32_t)env->CF << 31);
}
/* T1 based, set C flag */
void OPPROTO op_shll_T1_im_cc(void)
{
@ -512,6 +517,14 @@ void OPPROTO op_rorl_T1_im_cc(void)
T1 = ((uint32_t)T1 >> shift) | (T1 << (32 - shift));
}
void OPPROTO op_rrxl_T1_cc(void)
{
uint32_t c;
c = T1 & 1;
T1 = ((uint32_t)T1 >> 1) | ((uint32_t)env->CF << 31);
env->CF = c;
}
/* T2 based */
void OPPROTO op_shll_T2_im(void)
{

5
target-arm/translate.c
View File

@ -365,6 +365,11 @@ static void disas_arm_insn(DisasContext *s)
} else {
gen_shift_T1_im[shiftop](shift);
}
} else if (shiftop == 3) {
if (logic_cc)
gen_op_rrxl_T1_cc();
else
gen_op_rrxl_T1();
}
} else {
rs = (insn >> 8) & 0xf;