mirror of https://gitee.com/openkylin/qemu.git
target/m68k: add MC68040 MMU
Only add MC68040 MMU page table processing and related registers (Special Status Word, Translation Control Register, User Root Pointer and Supervisor Root Pointer). Transparent Translation Registers, DFC/SFC and pflush/ptest will be added later. Signed-off-by: Laurent Vivier <laurent@vivier.eu> Reviewed-by: Richard Henderson <richard.henderson@linaro.org> Message-Id: <20180118193846.24953-3-laurent@vivier.eu>
This commit is contained in:
Laurent Vivier
parent
98670d47cd
commit
88b2fef6c3
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@ -269,9 +269,9 @@ static void m68k_cpu_class_init(ObjectClass *c, void *data)
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cc->set_pc = m68k_cpu_set_pc;
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cc->gdb_read_register = m68k_cpu_gdb_read_register;
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cc->gdb_write_register = m68k_cpu_gdb_write_register;
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#ifdef CONFIG_USER_ONLY
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cc->handle_mmu_fault = m68k_cpu_handle_mmu_fault;
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#else
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#if defined(CONFIG_SOFTMMU)
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cc->do_unassigned_access = m68k_cpu_unassigned_access;
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cc->get_phys_page_debug = m68k_cpu_get_phys_page_debug;
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#endif
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cc->disas_set_info = m68k_cpu_disas_set_info;
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@ -116,6 +116,12 @@ typedef struct CPUM68KState {
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/* MMU status. */
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struct {
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uint32_t ar;
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uint32_t ssw;
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/* 68040 */
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uint16_t tcr;
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uint32_t urp;
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uint32_t srp;
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bool fault;
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} mmu;
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/* Control registers. */
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@ -226,6 +232,92 @@ typedef enum {
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#define M68K_USP 1
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#define M68K_ISP 2
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/* bits for 68040 special status word */
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#define M68K_CP_040 0x8000
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#define M68K_CU_040 0x4000
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#define M68K_CT_040 0x2000
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#define M68K_CM_040 0x1000
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#define M68K_MA_040 0x0800
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#define M68K_ATC_040 0x0400
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#define M68K_LK_040 0x0200
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#define M68K_RW_040 0x0100
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#define M68K_SIZ_040 0x0060
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#define M68K_TT_040 0x0018
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#define M68K_TM_040 0x0007
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#define M68K_TM_040_DATA 0x0001
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#define M68K_TM_040_CODE 0x0002
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#define M68K_TM_040_SUPER 0x0004
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/* bits for 68040 write back status word */
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#define M68K_WBV_040 0x80
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#define M68K_WBSIZ_040 0x60
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#define M68K_WBBYT_040 0x20
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#define M68K_WBWRD_040 0x40
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#define M68K_WBLNG_040 0x00
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#define M68K_WBTT_040 0x18
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#define M68K_WBTM_040 0x07
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/* bus access size codes */
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#define M68K_BA_SIZE_MASK 0x60
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#define M68K_BA_SIZE_BYTE 0x20
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#define M68K_BA_SIZE_WORD 0x40
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#define M68K_BA_SIZE_LONG 0x00
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#define M68K_BA_SIZE_LINE 0x60
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/* bus access transfer type codes */
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#define M68K_BA_TT_MOVE16 0x08
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/* bits for 68040 MMU status register (mmusr) */
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#define M68K_MMU_B_040 0x0800
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#define M68K_MMU_G_040 0x0400
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#define M68K_MMU_U1_040 0x0200
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#define M68K_MMU_U0_040 0x0100
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#define M68K_MMU_S_040 0x0080
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#define M68K_MMU_CM_040 0x0060
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#define M68K_MMU_M_040 0x0010
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#define M68K_MMU_WP_040 0x0004
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#define M68K_MMU_T_040 0x0002
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#define M68K_MMU_R_040 0x0001
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#define M68K_MMU_SR_MASK_040 (M68K_MMU_G_040 | M68K_MMU_U1_040 | \
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M68K_MMU_U0_040 | M68K_MMU_S_040 | \
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M68K_MMU_CM_040 | M68K_MMU_M_040 | \
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M68K_MMU_WP_040)
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/* bits for 68040 MMU Translation Control Register */
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#define M68K_TCR_ENABLED 0x8000
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#define M68K_TCR_PAGE_8K 0x4000
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/* bits for 68040 MMU Table Descriptor / Page Descriptor / TTR */
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#define M68K_DESC_WRITEPROT 0x00000004
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#define M68K_DESC_USED 0x00000008
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#define M68K_DESC_MODIFIED 0x00000010
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#define M68K_DESC_CACHEMODE 0x00000060
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#define M68K_DESC_CM_WRTHRU 0x00000000
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#define M68K_DESC_CM_COPYBK 0x00000020
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#define M68K_DESC_CM_SERIAL 0x00000040
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#define M68K_DESC_CM_NCACHE 0x00000060
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#define M68K_DESC_SUPERONLY 0x00000080
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#define M68K_DESC_USERATTR 0x00000300
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#define M68K_DESC_USERATTR_SHIFT 8
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#define M68K_DESC_GLOBAL 0x00000400
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#define M68K_DESC_URESERVED 0x00000800
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#define M68K_4K_PAGE_MASK (~0xff)
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#define M68K_POINTER_BASE(entry) (entry & ~0x1ff)
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#define M68K_ROOT_INDEX(addr) ((address >> 23) & 0x1fc)
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#define M68K_POINTER_INDEX(addr) ((address >> 16) & 0x1fc)
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#define M68K_4K_PAGE_BASE(entry) (next & M68K_4K_PAGE_MASK)
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#define M68K_4K_PAGE_INDEX(addr) ((address >> 10) & 0xfc)
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#define M68K_8K_PAGE_MASK (~0x7f)
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#define M68K_8K_PAGE_BASE(entry) (next & M68K_8K_PAGE_MASK)
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#define M68K_8K_PAGE_INDEX(addr) ((address >> 11) & 0x7c)
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#define M68K_UDT_VALID(entry) (entry & 2)
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#define M68K_PDT_VALID(entry) (entry & 3)
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#define M68K_PDT_INDIRECT(entry) ((entry & 3) == 2)
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#define M68K_INDIRECT_POINTER(addr) (addr & ~3)
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/* m68k Control Registers */
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/* ColdFire */
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@ -387,16 +479,23 @@ void m68k_cpu_list(FILE *f, fprintf_function cpu_fprintf);
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void register_m68k_insns (CPUM68KState *env);
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#ifdef CONFIG_USER_ONLY
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/* Coldfire Linux uses 8k pages
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* and m68k linux uses 4k pages
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* use the smaller one
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* use the smallest one
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*/
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#define TARGET_PAGE_BITS 12
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#else
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/* Smallest TLB entry size is 1k. */
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#define TARGET_PAGE_BITS 10
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#endif
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enum {
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/* 1 bit to define user level / supervisor access */
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ACCESS_SUPER = 0x01,
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/* 1 bit to indicate direction */
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ACCESS_STORE = 0x02,
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/* 1 bit to indicate debug access */
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ACCESS_DEBUG = 0x04,
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/* Type of instruction that generated the access */
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ACCESS_CODE = 0x10, /* Code fetch access */
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ACCESS_DATA = 0x20, /* Data load/store access */
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};
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#define TARGET_PHYS_ADDR_SPACE_BITS 32
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#define TARGET_VIRT_ADDR_SPACE_BITS 32
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@ -412,6 +511,7 @@ void register_m68k_insns (CPUM68KState *env);
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/* MMU modes definitions */
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#define MMU_MODE0_SUFFIX _kernel
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#define MMU_MODE1_SUFFIX _user
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#define MMU_KERNEL_IDX 0
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#define MMU_USER_IDX 1
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static inline int cpu_mmu_index (CPUM68KState *env, bool ifetch)
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{
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@ -420,6 +520,9 @@ static inline int cpu_mmu_index (CPUM68KState *env, bool ifetch)
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int m68k_cpu_handle_mmu_fault(CPUState *cpu, vaddr address, int size, int rw,
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int mmu_idx);
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void m68k_cpu_unassigned_access(CPUState *cs, hwaddr addr,
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bool is_write, bool is_exec, int is_asi,
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unsigned size);
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#include "exec/cpu-all.h"
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@ -212,6 +212,15 @@ void HELPER(m68k_movec_to)(CPUM68KState *env, uint32_t reg, uint32_t val)
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m68k_switch_sp(env);
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return;
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/* MC680[34]0 */
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case M68K_CR_TC:
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env->mmu.tcr = val;
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return;
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case M68K_CR_SRP:
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env->mmu.srp = val;
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return;
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case M68K_CR_URP:
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env->mmu.urp = val;
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return;
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case M68K_CR_USP:
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env->sp[M68K_USP] = val;
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return;
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@ -238,12 +247,19 @@ uint32_t HELPER(m68k_movec_from)(CPUM68KState *env, uint32_t reg)
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case M68K_CR_CACR:
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return env->cacr;
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/* MC680[34]0 */
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case M68K_CR_TC:
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return env->mmu.tcr;
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case M68K_CR_SRP:
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return env->mmu.srp;
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case M68K_CR_USP:
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return env->sp[M68K_USP];
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case M68K_CR_MSP:
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return env->sp[M68K_SSP];
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case M68K_CR_ISP:
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return env->sp[M68K_ISP];
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/* MC68040/MC68LC040 */
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case M68K_CR_URP:
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return env->mmu.urp;
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}
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cpu_abort(CPU(cpu), "Unimplemented control register read 0x%x\n",
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reg);
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@ -320,23 +336,215 @@ int m68k_cpu_handle_mmu_fault(CPUState *cs, vaddr address, int size, int rw,
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#else
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/* MMU */
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/* MMU: 68040 only */
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static int get_physical_address(CPUM68KState *env, hwaddr *physical,
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int *prot, target_ulong address,
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int access_type, target_ulong *page_size)
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{
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M68kCPU *cpu = m68k_env_get_cpu(env);
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CPUState *cs = CPU(cpu);
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uint32_t entry;
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uint32_t next;
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target_ulong page_mask;
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bool debug = access_type & ACCESS_DEBUG;
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int page_bits;
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/* Page Table Root Pointer */
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*prot = PAGE_READ | PAGE_WRITE;
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if (access_type & ACCESS_CODE) {
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*prot |= PAGE_EXEC;
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}
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if (access_type & ACCESS_SUPER) {
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next = env->mmu.srp;
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} else {
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next = env->mmu.urp;
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}
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/* Root Index */
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entry = M68K_POINTER_BASE(next) | M68K_ROOT_INDEX(address);
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next = ldl_phys(cs->as, entry);
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if (!M68K_UDT_VALID(next)) {
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return -1;
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}
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if (!(next & M68K_DESC_USED) && !debug) {
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stl_phys(cs->as, entry, next | M68K_DESC_USED);
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}
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if (next & M68K_DESC_WRITEPROT) {
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*prot &= ~PAGE_WRITE;
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if (access_type & ACCESS_STORE) {
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return -1;
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}
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}
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/* Pointer Index */
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entry = M68K_POINTER_BASE(next) | M68K_POINTER_INDEX(address);
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next = ldl_phys(cs->as, entry);
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if (!M68K_UDT_VALID(next)) {
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return -1;
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}
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if (!(next & M68K_DESC_USED) && !debug) {
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stl_phys(cs->as, entry, next | M68K_DESC_USED);
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}
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if (next & M68K_DESC_WRITEPROT) {
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*prot &= ~PAGE_WRITE;
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if (access_type & ACCESS_STORE) {
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return -1;
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}
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}
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/* Page Index */
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if (env->mmu.tcr & M68K_TCR_PAGE_8K) {
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entry = M68K_8K_PAGE_BASE(next) | M68K_8K_PAGE_INDEX(address);
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} else {
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entry = M68K_4K_PAGE_BASE(next) | M68K_4K_PAGE_INDEX(address);
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}
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next = ldl_phys(cs->as, entry);
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if (!M68K_PDT_VALID(next)) {
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return -1;
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}
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if (M68K_PDT_INDIRECT(next)) {
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next = ldl_phys(cs->as, M68K_INDIRECT_POINTER(next));
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}
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if (access_type & ACCESS_STORE) {
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if (next & M68K_DESC_WRITEPROT) {
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if (!(next & M68K_DESC_USED) && !debug) {
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stl_phys(cs->as, entry, next | M68K_DESC_USED);
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}
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} else if ((next & (M68K_DESC_MODIFIED | M68K_DESC_USED)) !=
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(M68K_DESC_MODIFIED | M68K_DESC_USED) && !debug) {
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stl_phys(cs->as, entry,
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next | (M68K_DESC_MODIFIED | M68K_DESC_USED));
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}
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} else {
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if (!(next & M68K_DESC_USED) && !debug) {
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stl_phys(cs->as, entry, next | M68K_DESC_USED);
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}
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}
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if (env->mmu.tcr & M68K_TCR_PAGE_8K) {
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page_bits = 13;
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} else {
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page_bits = 12;
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}
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*page_size = 1 << page_bits;
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page_mask = ~(*page_size - 1);
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*physical = next & page_mask;
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if (next & M68K_DESC_WRITEPROT) {
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*prot &= ~PAGE_WRITE;
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if (access_type & ACCESS_STORE) {
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return -1;
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}
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}
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if (next & M68K_DESC_SUPERONLY) {
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if ((access_type & ACCESS_SUPER) == 0) {
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return -1;
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}
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}
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return 0;
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}
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/* TODO: This will need fixing once the MMU is implemented. */
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hwaddr m68k_cpu_get_phys_page_debug(CPUState *cs, vaddr addr)
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{
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return addr;
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M68kCPU *cpu = M68K_CPU(cs);
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CPUM68KState *env = &cpu->env;
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hwaddr phys_addr;
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int prot;
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int access_type;
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target_ulong page_size;
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if ((env->mmu.tcr & M68K_TCR_ENABLED) == 0) {
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/* MMU disabled */
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return addr;
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}
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access_type = ACCESS_DATA | ACCESS_DEBUG;
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if (env->sr & SR_S) {
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access_type |= ACCESS_SUPER;
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}
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if (get_physical_address(env, &phys_addr, &prot,
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addr, access_type, &page_size) != 0) {
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return -1;
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}
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return phys_addr;
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}
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int m68k_cpu_handle_mmu_fault(CPUState *cs, vaddr address, int size, int rw,
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int mmu_idx)
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{
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M68kCPU *cpu = M68K_CPU(cs);
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CPUM68KState *env = &cpu->env;
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hwaddr physical;
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int prot;
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int access_type;
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int ret;
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target_ulong page_size;
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address &= TARGET_PAGE_MASK;
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prot = PAGE_READ | PAGE_WRITE | PAGE_EXEC;
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tlb_set_page(cs, address, address, prot, mmu_idx, TARGET_PAGE_SIZE);
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return 0;
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if ((env->mmu.tcr & M68K_TCR_ENABLED) == 0) {
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/* MMU disabled */
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tlb_set_page(cs, address & TARGET_PAGE_MASK,
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address & TARGET_PAGE_MASK,
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PAGE_READ | PAGE_WRITE | PAGE_EXEC,
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mmu_idx, TARGET_PAGE_SIZE);
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return 0;
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}
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if (rw == 2) {
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access_type = ACCESS_CODE;
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rw = 0;
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} else {
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access_type = ACCESS_DATA;
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if (rw) {
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access_type |= ACCESS_STORE;
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}
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}
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if (mmu_idx != MMU_USER_IDX) {
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access_type |= ACCESS_SUPER;
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}
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ret = get_physical_address(&cpu->env, &physical, &prot,
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address, access_type, &page_size);
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if (ret == 0) {
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address &= TARGET_PAGE_MASK;
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physical += address & (page_size - 1);
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tlb_set_page(cs, address, physical,
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prot, mmu_idx, TARGET_PAGE_SIZE);
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return 0;
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}
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/* page fault */
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env->mmu.ssw = M68K_ATC_040;
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switch (size) {
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case 1:
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env->mmu.ssw |= M68K_BA_SIZE_BYTE;
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break;
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case 2:
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env->mmu.ssw |= M68K_BA_SIZE_WORD;
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break;
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case 4:
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env->mmu.ssw |= M68K_BA_SIZE_LONG;
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break;
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}
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if (access_type & ACCESS_SUPER) {
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env->mmu.ssw |= M68K_TM_040_SUPER;
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}
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if (access_type & ACCESS_CODE) {
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env->mmu.ssw |= M68K_TM_040_CODE;
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} else {
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env->mmu.ssw |= M68K_TM_040_DATA;
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}
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if (!(access_type & ACCESS_STORE)) {
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env->mmu.ssw |= M68K_RW_040;
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}
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env->mmu.ar = address;
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cs->exception_index = EXCP_ACCESS;
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||||
return 1;
|
||||
}
|
||||
|
||||
/* Notify CPU of a pending interrupt. Prioritization and vectoring should
|
||||
|
|
|
|||
|
|
@ -31,6 +31,8 @@ static const MonitorDef monitor_defs[] = {
|
|||
{ "ssp", offsetof(CPUM68KState, sp[0]) },
|
||||
{ "usp", offsetof(CPUM68KState, sp[1]) },
|
||||
{ "isp", offsetof(CPUM68KState, sp[2]) },
|
||||
{ "urp", offsetof(CPUM68KState, mmu.urp) },
|
||||
{ "srp", offsetof(CPUM68KState, mmu.srp) },
|
||||
{ NULL },
|
||||
};
|
||||
|
||||
|
|
|
|||
|
|
@ -360,7 +360,49 @@ static void m68k_interrupt_all(CPUM68KState *env, int is_hw)
|
|||
sp = env->aregs[7];
|
||||
|
||||
sp &= ~1;
|
||||
if (cs->exception_index == EXCP_ADDRESS) {
|
||||
if (cs->exception_index == EXCP_ACCESS) {
|
||||
if (env->mmu.fault) {
|
||||
cpu_abort(cs, "DOUBLE MMU FAULT\n");
|
||||
}
|
||||
env->mmu.fault = true;
|
||||
sp -= 4;
|
||||
cpu_stl_kernel(env, sp, 0); /* push data 3 */
|
||||
sp -= 4;
|
||||
cpu_stl_kernel(env, sp, 0); /* push data 2 */
|
||||
sp -= 4;
|
||||
cpu_stl_kernel(env, sp, 0); /* push data 1 */
|
||||
sp -= 4;
|
||||
cpu_stl_kernel(env, sp, 0); /* write back 1 / push data 0 */
|
||||
sp -= 4;
|
||||
cpu_stl_kernel(env, sp, 0); /* write back 1 address */
|
||||
sp -= 4;
|
||||
cpu_stl_kernel(env, sp, 0); /* write back 2 data */
|
||||
sp -= 4;
|
||||
cpu_stl_kernel(env, sp, 0); /* write back 2 address */
|
||||
sp -= 4;
|
||||
cpu_stl_kernel(env, sp, 0); /* write back 3 data */
|
||||
sp -= 4;
|
||||
cpu_stl_kernel(env, sp, env->mmu.ar); /* write back 3 address */
|
||||
sp -= 4;
|
||||
cpu_stl_kernel(env, sp, env->mmu.ar); /* fault address */
|
||||
sp -= 2;
|
||||
cpu_stw_kernel(env, sp, 0); /* write back 1 status */
|
||||
sp -= 2;
|
||||
cpu_stw_kernel(env, sp, 0); /* write back 2 status */
|
||||
sp -= 2;
|
||||
cpu_stw_kernel(env, sp, 0); /* write back 3 status */
|
||||
sp -= 2;
|
||||
cpu_stw_kernel(env, sp, env->mmu.ssw); /* special status word */
|
||||
sp -= 4;
|
||||
cpu_stl_kernel(env, sp, env->mmu.ar); /* effective address */
|
||||
do_stack_frame(env, &sp, 7, oldsr, 0, retaddr);
|
||||
env->mmu.fault = false;
|
||||
if (qemu_loglevel_mask(CPU_LOG_INT)) {
|
||||
qemu_log(" "
|
||||
"ssw: %08x ea: %08x\n",
|
||||
env->mmu.ssw, env->mmu.ar);
|
||||
}
|
||||
} else if (cs->exception_index == EXCP_ADDRESS) {
|
||||
do_stack_frame(env, &sp, 2, oldsr, 0, retaddr);
|
||||
} else if (cs->exception_index == EXCP_ILLEGAL ||
|
||||
cs->exception_index == EXCP_DIV0 ||
|
||||
|
|
@ -408,6 +450,56 @@ static inline void do_interrupt_m68k_hardirq(CPUM68KState *env)
|
|||
{
|
||||
do_interrupt_all(env, 1);
|
||||
}
|
||||
|
||||
void m68k_cpu_unassigned_access(CPUState *cs, hwaddr addr, bool is_write,
|
||||
bool is_exec, int is_asi, unsigned size)
|
||||
{
|
||||
M68kCPU *cpu = M68K_CPU(cs);
|
||||
CPUM68KState *env = &cpu->env;
|
||||
#ifdef DEBUG_UNASSIGNED
|
||||
qemu_log_mask(CPU_LOG_INT, "Unassigned " TARGET_FMT_plx " wr=%d exe=%d\n",
|
||||
addr, is_write, is_exec);
|
||||
#endif
|
||||
if (env == NULL) {
|
||||
/* when called from gdb, env is NULL */
|
||||
return;
|
||||
}
|
||||
|
||||
if (m68k_feature(env, M68K_FEATURE_M68040)) {
|
||||
env->mmu.ssw |= M68K_ATC_040;
|
||||
/* FIXME: manage MMU table access error */
|
||||
env->mmu.ssw &= ~M68K_TM_040;
|
||||
if (env->sr & SR_S) { /* SUPERVISOR */
|
||||
env->mmu.ssw |= M68K_TM_040_SUPER;
|
||||
}
|
||||
if (is_exec) { /* instruction or data */
|
||||
env->mmu.ssw |= M68K_TM_040_CODE;
|
||||
} else {
|
||||
env->mmu.ssw |= M68K_TM_040_DATA;
|
||||
}
|
||||
env->mmu.ssw &= ~M68K_BA_SIZE_MASK;
|
||||
switch (size) {
|
||||
case 1:
|
||||
env->mmu.ssw |= M68K_BA_SIZE_BYTE;
|
||||
break;
|
||||
case 2:
|
||||
env->mmu.ssw |= M68K_BA_SIZE_WORD;
|
||||
break;
|
||||
case 4:
|
||||
env->mmu.ssw |= M68K_BA_SIZE_LONG;
|
||||
break;
|
||||
}
|
||||
|
||||
if (!is_write) {
|
||||
env->mmu.ssw |= M68K_RW_040;
|
||||
}
|
||||
|
||||
env->mmu.ar = addr;
|
||||
|
||||
cs->exception_index = EXCP_ACCESS;
|
||||
cpu_loop_exit(cs);
|
||||
}
|
||||
}
|
||||
#endif
|
||||
|
||||
bool m68k_cpu_exec_interrupt(CPUState *cs, int interrupt_request)
|
||||
|
|
|
|||
|
|
@ -5980,6 +5980,8 @@ void m68k_cpu_dump_state(CPUState *cs, FILE *f, fprintf_function cpu_fprintf,
|
|||
env->current_sp == M68K_USP ? "->" : " ", env->sp[M68K_USP],
|
||||
env->current_sp == M68K_ISP ? "->" : " ", env->sp[M68K_ISP]);
|
||||
cpu_fprintf(f, "VBR = 0x%08x\n", env->vbr);
|
||||
cpu_fprintf(f, "SSW %08x TCR %08x URP %08x SRP %08x\n",
|
||||
env->mmu.ssw, env->mmu.tcr, env->mmu.urp, env->mmu.srp);
|
||||
#endif
|
||||
}
|
||||
|
||||
|
|
|
|||
Loading…
Reference in New Issue