mirror of https://gitee.com/openkylin/qemu.git
target-arm: make IFSR banked
When EL3 is running in AArch32 (or ARMv7 with Security Extensions) IFSR has a secure and a non-secure instance. Adds IFSR32_EL2 definition and storage. Signed-off-by: Fabian Aggeler <aggelerf@ethz.ch> Signed-off-by: Greg Bellows <greg.bellows@linaro.org> Reviewed-by: Peter Maydell <peter.maydell@linaro.org> Message-id: 1416242878-876-20-git-send-email-greg.bellows@linaro.org Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
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@ -242,7 +242,15 @@ typedef struct CPUARMState {
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uint32_t pmsav5_insn_ap; /* PMSAv5 MPU insn access permissions */
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uint64_t hcr_el2; /* Hypervisor configuration register */
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uint64_t scr_el3; /* Secure configuration register. */
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uint32_t ifsr_el2; /* Fault status registers. */
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union { /* Fault status registers. */
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struct {
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uint64_t ifsr_ns;
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uint64_t ifsr_s;
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};
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struct {
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uint64_t ifsr32_el2;
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};
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};
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uint64_t esr_el[4];
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uint32_t c6_region[8]; /* MPU base/size registers. */
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uint64_t far_el[4]; /* Fault address registers. */
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@ -1654,8 +1654,9 @@ static const ARMCPRegInfo vmsa_cp_reginfo[] = {
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.fieldoffset = offsetoflow32(CPUARMState, cp15.esr_el[1]),
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.resetfn = arm_cp_reset_ignore, },
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{ .name = "IFSR", .cp = 15, .crn = 5, .crm = 0, .opc1 = 0, .opc2 = 1,
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.access = PL1_RW,
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.fieldoffset = offsetof(CPUARMState, cp15.ifsr_el2), .resetvalue = 0, },
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.access = PL1_RW, .resetvalue = 0,
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.bank_fieldoffsets = { offsetoflow32(CPUARMState, cp15.ifsr_s),
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offsetoflow32(CPUARMState, cp15.ifsr_ns) } },
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{ .name = "ESR_EL1", .state = ARM_CP_STATE_AA64,
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.opc0 = 3, .crn = 5, .crm = 2, .opc1 = 0, .opc2 = 0,
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.access = PL1_RW,
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@ -2347,6 +2348,10 @@ static const ARMCPRegInfo v8_el2_cp_reginfo[] = {
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.type = ARM_CP_NO_MIGRATE,
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.opc0 = 3, .opc1 = 4, .crn = 5, .crm = 2, .opc2 = 0,
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.access = PL2_RW, .fieldoffset = offsetof(CPUARMState, cp15.esr_el[2]) },
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{ .name = "IFSR32_EL2", .state = ARM_CP_STATE_AA64,
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.opc0 = 3, .opc1 = 4, .crn = 5, .crm = 0, .opc2 = 1,
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.access = PL2_RW, .resetvalue = 0,
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.fieldoffset = offsetof(CPUARMState, cp15.ifsr32_el2) },
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{ .name = "FAR_EL2", .state = ARM_CP_STATE_AA64,
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.opc0 = 3, .opc1 = 4, .crn = 6, .crm = 0, .opc2 = 0,
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.access = PL2_RW, .fieldoffset = offsetof(CPUARMState, cp15.far_el[2]) },
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@ -4323,11 +4328,11 @@ void arm_cpu_do_interrupt(CPUState *cs)
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env->exception.fsr = 2;
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/* Fall through to prefetch abort. */
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case EXCP_PREFETCH_ABORT:
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env->cp15.ifsr_el2 = env->exception.fsr;
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A32_BANKED_CURRENT_REG_SET(env, ifsr, env->exception.fsr);
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env->cp15.far_el[1] = deposit64(env->cp15.far_el[1], 32, 32,
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env->exception.vaddress);
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qemu_log_mask(CPU_LOG_INT, "...with IFSR 0x%x IFAR 0x%x\n",
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env->cp15.ifsr_el2, (uint32_t)env->exception.vaddress);
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env->exception.fsr, (uint32_t)env->exception.vaddress);
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new_mode = ARM_CPU_MODE_ABT;
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addr = 0x0c;
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mask = CPSR_A | CPSR_I;
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