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docs: update ivshmem device spec
Add some notes on the parts needed to use ivshmem devices: more specifically, explain the purpose of an ivshmem server and the basic concept to use the ivshmem devices in guests. Move some parts of the documentation and re-organise it. Signed-off-by: David Marchand <david.marchand@6wind.com> Reviewed-by: Claudio Fontana <claudio.fontana@huawei.com> Reviewed-by: Stefan Hajnoczi <stefanha@redhat.com> Signed-off-by: Marc-André Lureau <marcandre.lureau@redhat.com>
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David Marchand
Marc-André Lureau
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8c4ef202b9
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@ -2,30 +2,103 @@
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Device Specification for Inter-VM shared memory device
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------------------------------------------------------
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The Inter-VM shared memory device is designed to share a region of memory to
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userspace in multiple virtual guests. The memory region does not belong to any
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guest, but is a POSIX memory object on the host. Optionally, the device may
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support sending interrupts to other guests sharing the same memory region.
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The Inter-VM shared memory device is designed to share a memory region (created
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on the host via the POSIX shared memory API) between multiple QEMU processes
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running different guests. In order for all guests to be able to pick up the
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shared memory area, it is modeled by QEMU as a PCI device exposing said memory
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to the guest as a PCI BAR.
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The memory region does not belong to any guest, but is a POSIX memory object on
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the host. The host can access this shared memory if needed.
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The device also provides an optional communication mechanism between guests
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sharing the same memory object. More details about that in the section 'Guest to
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guest communication' section.
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The Inter-VM PCI device
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-----------------------
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*BARs*
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From the VM point of view, the ivshmem PCI device supports three BARs.
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The device supports three BARs. BAR0 is a 1 Kbyte MMIO region to support
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registers. BAR1 is used for MSI-X when it is enabled in the device. BAR2 is
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used to map the shared memory object from the host. The size of BAR2 is
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specified when the guest is started and must be a power of 2 in size.
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- BAR0 is a 1 Kbyte MMIO region to support registers and interrupts when MSI is
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not used.
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- BAR1 is used for MSI-X when it is enabled in the device.
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- BAR2 is used to access the shared memory object.
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*Registers*
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It is your choice how to use the device but you must choose between two
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behaviors :
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The device currently supports 4 registers of 32-bits each. Registers
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are used for synchronization between guests sharing the same memory object when
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interrupts are supported (this requires using the shared memory server).
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- basically, if you only need the shared memory part, you will map BAR2.
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This way, you have access to the shared memory in guest and can use it as you
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see fit (memnic, for example, uses it in userland
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http://dpdk.org/browse/memnic).
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The server assigns each VM an ID number and sends this ID number to the QEMU
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process when the guest starts.
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- BAR0 and BAR1 are used to implement an optional communication mechanism
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through interrupts in the guests. If you need an event mechanism between the
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guests accessing the shared memory, you will most likely want to write a
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kernel driver that will handle interrupts. See details in the section 'Guest
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to guest communication' section.
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The behavior is chosen when starting your QEMU processes:
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- no communication mechanism needed, the first QEMU to start creates the shared
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memory on the host, subsequent QEMU processes will use it.
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- communication mechanism needed, an ivshmem server must be started before any
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QEMU processes, then each QEMU process connects to the server unix socket.
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For more details on the QEMU ivshmem parameters, see qemu-doc documentation.
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Guest to guest communication
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----------------------------
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This section details the communication mechanism between the guests accessing
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the ivhsmem shared memory.
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*ivshmem server*
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This server code is available in qemu.git/contrib/ivshmem-server.
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The server must be started on the host before any guest.
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It creates a shared memory object then waits for clients to connect on a unix
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socket.
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For each client (QEMU process) that connects to the server:
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- the server assigns an ID for this client and sends this ID to him as the first
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message,
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- the server sends a fd to the shared memory object to this client,
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- the server creates a new set of host eventfds associated to the new client and
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sends this set to all already connected clients,
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- finally, the server sends all the eventfds sets for all clients to the new
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client.
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The server signals all clients when one of them disconnects.
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The client IDs are limited to 16 bits because of the current implementation (see
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Doorbell register in 'PCI device registers' subsection). Hence only 65536
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clients are supported.
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All the file descriptors (fd to the shared memory, eventfds for each client)
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are passed to clients using SCM_RIGHTS over the server unix socket.
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Apart from the current ivshmem implementation in QEMU, an ivshmem client has
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been provided in qemu.git/contrib/ivshmem-client for debug.
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*QEMU as an ivshmem client*
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At initialisation, when creating the ivshmem device, QEMU gets its ID from the
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server then makes it available through BAR0 IVPosition register for the VM to
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use (see 'PCI device registers' subsection).
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QEMU then uses the fd to the shared memory to map it to BAR2.
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eventfds for all other clients received from the server are stored to implement
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BAR0 Doorbell register (see 'PCI device registers' subsection).
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Finally, eventfds assigned to this QEMU process are used to send interrupts in
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this VM.
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*PCI device registers*
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From the VM point of view, the ivshmem PCI device supports 4 registers of
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32-bits each.
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enum ivshmem_registers {
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IntrMask = 0,
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@ -49,8 +122,8 @@ bit to 0 and unmasked by setting the first bit to 1.
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IVPosition Register: The IVPosition register is read-only and reports the
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guest's ID number. The guest IDs are non-negative integers. When using the
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server, since the server is a separate process, the VM ID will only be set when
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the device is ready (shared memory is received from the server and accessible via
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the device). If the device is not ready, the IVPosition will return -1.
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the device is ready (shared memory is received from the server and accessible
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via the device). If the device is not ready, the IVPosition will return -1.
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Applications should ensure that they have a valid VM ID before accessing the
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shared memory.
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@ -59,8 +132,8 @@ Doorbell register. The doorbell register is 32-bits, logically divided into
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two 16-bit fields. The high 16-bits are the guest ID to interrupt and the low
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16-bits are the interrupt vector to trigger. The semantics of the value
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written to the doorbell depends on whether the device is using MSI or a regular
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pin-based interrupt. In short, MSI uses vectors while regular interrupts set the
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status register.
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pin-based interrupt. In short, MSI uses vectors while regular interrupts set
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the status register.
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Regular Interrupts
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@ -71,7 +144,7 @@ interrupt in the destination guest.
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Message Signalled Interrupts
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A ivshmem device may support multiple MSI vectors. If so, the lower 16-bits
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An ivshmem device may support multiple MSI vectors. If so, the lower 16-bits
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written to the Doorbell register must be between 0 and the maximum number of
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vectors the guest supports. The lower 16 bits written to the doorbell is the
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MSI vector that will be raised in the destination guest. The number of MSI
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@ -83,14 +156,3 @@ interrupt itself should be communicated via the shared memory region. Devices
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supporting multiple MSI vectors can use different vectors to indicate different
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events have occurred. The semantics of interrupt vectors are left to the
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user's discretion.
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Usage in the Guest
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------------------
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The shared memory device is intended to be used with the provided UIO driver.
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Very little configuration is needed. The guest should map BAR0 to access the
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registers (an array of 32-bit ints allows simple writing) and map BAR2 to
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access the shared memory region itself. The size of the shared memory region
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is specified when the guest (or shared memory server) is started. A guest may
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map the whole shared memory region or only part of it.
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