mirror of https://gitee.com/openkylin/qemu.git
arm support - modified sparc to work with direct chaining
git-svn-id: svn://svn.savannah.nongnu.org/qemu/trunk@218 c046a42c-6fe2-441c-8c8c-71466251a162
This commit is contained in:
bellard
parent
2d0e9143e2
commit
8c6939c0b0
134
exec-i386.c
134
exec-i386.c
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@ -25,58 +25,6 @@
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/* main execution loop */
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/* thread support */
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spinlock_t global_cpu_lock = SPIN_LOCK_UNLOCKED;
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void cpu_lock(void)
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{
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spin_lock(&global_cpu_lock);
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}
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void cpu_unlock(void)
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{
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spin_unlock(&global_cpu_lock);
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}
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void cpu_loop_exit(void)
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{
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/* NOTE: the register at this point must be saved by hand because
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longjmp restore them */
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#ifdef __sparc__
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/* We have to stay in the same register window as our caller,
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* thus this trick.
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*/
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__asm__ __volatile__("restore\n\t"
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"mov\t%o0, %i0");
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#endif
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#ifdef reg_EAX
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env->regs[R_EAX] = EAX;
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#endif
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#ifdef reg_ECX
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env->regs[R_ECX] = ECX;
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#endif
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#ifdef reg_EDX
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env->regs[R_EDX] = EDX;
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#endif
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#ifdef reg_EBX
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env->regs[R_EBX] = EBX;
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#endif
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#ifdef reg_ESP
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env->regs[R_ESP] = ESP;
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#endif
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#ifdef reg_EBP
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env->regs[R_EBP] = EBP;
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#endif
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#ifdef reg_ESI
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env->regs[R_ESI] = ESI;
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#endif
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#ifdef reg_EDI
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env->regs[R_EDI] = EDI;
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#endif
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longjmp(env->jmp_env, 1);
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}
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int cpu_x86_exec(CPUX86State *env1)
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{
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int saved_T0, saved_T1, saved_A0;
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@ -104,13 +52,16 @@ int cpu_x86_exec(CPUX86State *env1)
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#endif
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#ifdef reg_EDI
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int saved_EDI;
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#endif
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#ifdef __sparc__
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int saved_i7, tmp_T0;
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#endif
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int code_gen_size, ret;
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void (*gen_func)(void);
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TranslationBlock *tb, **ptb;
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uint8_t *tc_ptr, *cs_base, *pc;
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unsigned int flags;
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/* first we save global registers */
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saved_T0 = T0;
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saved_T1 = T1;
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@ -149,6 +100,10 @@ int cpu_x86_exec(CPUX86State *env1)
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saved_EDI = EDI;
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EDI = env->regs[R_EDI];
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#endif
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#ifdef __sparc__
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/* we also save i7 because longjmp may not restore it */
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asm volatile ("mov %%i7, %0" : "=r" (saved_i7));
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#endif
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/* put eflags in CPU temporary format */
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CC_SRC = env->eflags & (CC_O | CC_S | CC_Z | CC_A | CC_P | CC_C);
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@ -161,6 +116,10 @@ int cpu_x86_exec(CPUX86State *env1)
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if (setjmp(env->jmp_env) == 0) {
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T0 = 0; /* force lookup of first TB */
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for(;;) {
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#ifdef __sparc__
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/* g1 can be modified by some libc? functions */
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tmp_T0 = T0;
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#endif
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if (env->interrupt_request) {
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env->exception_index = EXCP_INTERRUPT;
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cpu_loop_exit();
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@ -240,23 +199,32 @@ int cpu_x86_exec(CPUX86State *env1)
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lookup_symbol((void *)tb->pc));
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}
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#endif
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#ifdef __sparc__
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T0 = tmp_T0;
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#endif
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/* see if we can patch the calling TB */
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if (T0 != 0 && !(env->eflags & TF_MASK)) {
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spin_lock(&tb_lock);
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tb_add_jump((TranslationBlock *)(T0 & ~3), T0 & 3, tb);
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spin_unlock(&tb_lock);
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}
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tc_ptr = tb->tc_ptr;
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/* execute the generated code */
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gen_func = (void *)tc_ptr;
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#ifdef __sparc__
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#if defined(__sparc__)
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__asm__ __volatile__("call %0\n\t"
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" mov %%o7,%%i0"
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"mov %%o7,%%i0"
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: /* no outputs */
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: "r" (gen_func)
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: "i0", "i1", "i2", "i3", "i4", "i5");
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#elif defined(__arm__)
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asm volatile ("mov pc, %0\n\t"
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".global exec_loop\n\t"
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"exec_loop:\n\t"
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: /* no outputs */
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: "r" (gen_func)
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: "r1", "r2", "r3", "r8", "r9", "r10", "r12", "r14");
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#else
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gen_func();
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#endif
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@ -291,6 +259,9 @@ int cpu_x86_exec(CPUX86State *env1)
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#endif
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#ifdef reg_EDI
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EDI = saved_EDI;
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#endif
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#ifdef __sparc__
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asm volatile ("mov %0, %%i7" : : "r" (saved_i7));
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#endif
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T0 = saved_T0;
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T1 = saved_T1;
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@ -457,6 +428,7 @@ int cpu_x86_signal_handler(int host_signum, struct siginfo *info,
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uint32_t insn = *pc;
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int is_write = 0;
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/* XXX: need kernel patch to get write flag faster */
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switch (insn >> 26) {
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case 0x0d: // stw
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case 0x0e: // stb
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@ -475,6 +447,56 @@ int cpu_x86_signal_handler(int host_signum, struct siginfo *info,
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return handle_cpu_signal(pc, (unsigned long)info->si_addr,
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is_write, &uc->uc_sigmask);
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}
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#elif defined(__sparc__)
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int cpu_x86_signal_handler(int host_signum, struct siginfo *info,
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void *puc)
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{
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uint32_t *regs = (uint32_t *)(info + 1);
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void *sigmask = (regs + 20);
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unsigned long pc;
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int is_write;
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uint32_t insn;
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/* XXX: is there a standard glibc define ? */
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pc = regs[1];
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/* XXX: need kernel patch to get write flag faster */
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is_write = 0;
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insn = *(uint32_t *)pc;
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if ((insn >> 30) == 3) {
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switch((insn >> 19) & 0x3f) {
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case 0x05: // stb
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case 0x06: // sth
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case 0x04: // st
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case 0x07: // std
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case 0x24: // stf
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case 0x27: // stdf
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case 0x25: // stfsr
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is_write = 1;
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break;
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}
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}
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return handle_cpu_signal(pc, (unsigned long)info->si_addr,
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is_write, sigmask);
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}
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#elif defined(__arm__)
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int cpu_x86_signal_handler(int host_signum, struct siginfo *info,
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void *puc)
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{
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struct ucontext *uc = puc;
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unsigned long pc;
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int is_write;
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pc = uc->uc_mcontext.gregs[R15];
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/* XXX: compute is_write */
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is_write = 0;
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return handle_cpu_signal(pc, (unsigned long)info->si_addr,
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is_write,
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&uc->uc_sigmask);
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}
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#else
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#error CPU specific signal handler needed
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