mirror of https://gitee.com/openkylin/qemu.git
Misc fixes (Herve Poussineau)
- Fix internal fifo size (16 bytes), according to http://www.ibiblio.org/pub/historic-linux/early-ports/Sparc/NCR/NCR53C9X.txt - Fix values of STAT_MI and STAT_MO - Give a scsi ID to adapter, and prevent this ID to be used by devices - Prevent fifo overrun in esp_mem_writeb - Add a ESP_ERROR macro, and use it where appropriate git-svn-id: svn://svn.savannah.nongnu.org/qemu/trunk@5811 c046a42c-6fe2-441c-8c8c-71466251a162
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ce802585a9
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35
hw/esp.c
35
hw/esp.c
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@ -44,8 +44,11 @@ do { printf("ESP: " fmt , ##args); } while (0)
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#define DPRINTF(fmt, args...) do {} while (0)
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#endif
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#define ESP_ERROR(fmt, args...) \
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do { printf("ESP ERROR: %s: " fmt, __func__ , ##args); } while (0)
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#define ESP_REGS 16
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#define TI_BUFSZ 32
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#define TI_BUFSZ 16
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typedef struct ESPState ESPState;
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@ -120,8 +123,8 @@ struct ESPState {
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#define STAT_DI 0x01
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#define STAT_CD 0x02
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#define STAT_ST 0x03
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#define STAT_MI 0x06
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#define STAT_MO 0x07
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#define STAT_MO 0x06
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#define STAT_MI 0x07
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#define STAT_PIO_MASK 0x06
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#define STAT_TC 0x10
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@ -129,6 +132,8 @@ struct ESPState {
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#define STAT_GE 0x40
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#define STAT_INT 0x80
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#define BUSID_DID 0x07
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#define INTR_FC 0x08
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#define INTR_BS 0x10
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#define INTR_DC 0x20
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@ -165,7 +170,7 @@ static uint32_t get_cmd(ESPState *s, uint8_t *buf)
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int target;
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dmalen = s->rregs[ESP_TCLO] | (s->rregs[ESP_TCMID] << 8);
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target = s->wregs[ESP_WBUSID] & 7;
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target = s->wregs[ESP_WBUSID] & BUSID_DID;
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DPRINTF("get_cmd: len %d target %d\n", dmalen, target);
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if (s->dma) {
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s->dma_memory_read(s->dma_opaque, buf, dmalen);
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@ -318,7 +323,7 @@ static void esp_do_dma(ESPState *s)
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} else {
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s->current_dev->read_data(s->current_dev, 0);
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/* If there is still data to be read from the device then
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complete the DMA operation immeriately. Otherwise defer
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complete the DMA operation immediately. Otherwise defer
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until the scsi layer has completed. */
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if (s->dma_left == 0 && s->ti_size > 0) {
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esp_dma_done(s);
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@ -407,6 +412,8 @@ static void esp_reset(void *opaque)
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s->ti_wptr = 0;
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s->dma = 0;
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s->do_cmd = 0;
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s->rregs[ESP_CFG1] = 7;
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}
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static void parent_esp_reset(void *opaque, int irq, int level)
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@ -427,8 +434,8 @@ static uint32_t esp_mem_readb(void *opaque, target_phys_addr_t addr)
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if (s->ti_size > 0) {
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s->ti_size--;
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if ((s->rregs[ESP_RSTAT] & STAT_PIO_MASK) == 0) {
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/* Data in/out. */
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fprintf(stderr, "esp: PIO data read not implemented\n");
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/* Data out. */
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ESP_ERROR("PIO data read not implemented\n");
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s->rregs[ESP_FIFO] = 0;
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} else {
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s->rregs[ESP_FIFO] = s->ti_buf[s->ti_rptr++];
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@ -467,11 +474,8 @@ static void esp_mem_writeb(void *opaque, target_phys_addr_t addr, uint32_t val)
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case ESP_FIFO:
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if (s->do_cmd) {
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s->cmdbuf[s->cmdlen++] = val & 0xff;
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} else if ((s->rregs[ESP_RSTAT] & STAT_PIO_MASK) == 0) {
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uint8_t buf;
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buf = val & 0xff;
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s->ti_size--;
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fprintf(stderr, "esp: PIO data write not implemented\n");
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} else if (s->ti_size == TI_BUFSZ - 1) {
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ESP_ERROR("fifo overrun\n");
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} else {
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s->ti_size++;
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s->ti_buf[s->ti_wptr++] = val & 0xff;
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@ -537,7 +541,7 @@ static void esp_mem_writeb(void *opaque, target_phys_addr_t addr, uint32_t val)
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DPRINTF("Enable selection (%2.2x)\n", val);
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break;
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default:
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DPRINTF("Unhandled ESP command (%2.2x)\n", val);
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ESP_ERROR("Unhandled ESP command (%2.2x)\n", val);
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break;
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}
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break;
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@ -555,7 +559,8 @@ static void esp_mem_writeb(void *opaque, target_phys_addr_t addr, uint32_t val)
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s->rregs[saddr] = val;
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break;
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default:
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break;
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ESP_ERROR("invalid write of 0x%02x at [0x%x]\n", val, saddr);
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return;
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}
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s->wregs[saddr] = val;
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}
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@ -620,6 +625,8 @@ void esp_scsi_attach(void *opaque, BlockDriverState *bd, int id)
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if (id < 0) {
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for (id = 0; id < ESP_MAX_DEVS; id++) {
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if (id == (s->rregs[ESP_CFG1] & 0x7))
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continue;
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if (s->scsi_dev[id] == NULL)
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break;
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}
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