mirror of https://gitee.com/openkylin/qemu.git
PPC: Unify dcbzl code path
The bit that makes a dcbz instruction a dcbzl instruction was declared as reserved in ppc32 ISAs. However, hardware simply ignores the bit, making code valid if it simply invokes dcbzl instead of dcbz even on 750 and G4. Thus, mark the bit as unreserved so that we properly emulate a simple dcbz in case we're running on non-G5s. While at it, also refactor the code to check the 970 special case during runtime. This way we don't need to differenciate between a 970 dcbz and any other dcbz anymore. We also allow for future improvements to add e500mc dcbz handling. Reported-by: Amadeusz Sławiński <amade@asmblr.net> Signed-off-by: Alexander Graf <agraf@suse.de>
This commit is contained in:
Alexander Graf
parent
6b2578d678
commit
8e33944f8c
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@ -1857,10 +1857,8 @@ enum {
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PPC_CACHE = 0x0000000200000000ULL,
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/* icbi instruction */
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PPC_CACHE_ICBI = 0x0000000400000000ULL,
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/* dcbz instruction with fixed cache line size */
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/* dcbz instruction */
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PPC_CACHE_DCBZ = 0x0000000800000000ULL,
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/* dcbz instruction with tunable cache line size */
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PPC_CACHE_DCBZT = 0x0000001000000000ULL,
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/* dcba instruction */
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PPC_CACHE_DCBA = 0x0000002000000000ULL,
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/* Freescale cache locking instructions */
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@ -1928,7 +1926,7 @@ enum {
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| PPC_MEM_TLBIE | PPC_MEM_TLBSYNC \
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| PPC_MEM_SYNC | PPC_MEM_EIEIO \
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| PPC_CACHE | PPC_CACHE_ICBI \
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| PPC_CACHE_DCBZ | PPC_CACHE_DCBZT \
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| PPC_CACHE_DCBZ \
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| PPC_CACHE_DCBA | PPC_CACHE_LOCK \
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| PPC_EXTERN | PPC_SEGMENT | PPC_6xx_TLB \
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| PPC_74xx_TLB | PPC_40x_TLB | PPC_SEGMENT_64B \
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@ -25,8 +25,7 @@ DEF_HELPER_3(stmw, void, env, tl, i32)
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DEF_HELPER_4(lsw, void, env, tl, i32, i32)
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DEF_HELPER_5(lswx, void, env, tl, i32, i32, i32)
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DEF_HELPER_4(stsw, void, env, tl, i32, i32)
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DEF_HELPER_2(dcbz, void, env, tl)
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DEF_HELPER_2(dcbz_970, void, env, tl)
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DEF_HELPER_3(dcbz, void, env, tl, i32)
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DEF_HELPER_2(icbi, void, env, tl)
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DEF_HELPER_5(lscbx, tl, env, tl, i32, i32, i32)
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@ -136,18 +136,21 @@ static void do_dcbz(CPUPPCState *env, target_ulong addr, int dcache_line_size)
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}
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}
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void helper_dcbz(CPUPPCState *env, target_ulong addr)
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void helper_dcbz(CPUPPCState *env, target_ulong addr, uint32_t is_dcbzl)
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{
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do_dcbz(env, addr, env->dcache_line_size);
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}
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int dcbz_size = env->dcache_line_size;
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void helper_dcbz_970(CPUPPCState *env, target_ulong addr)
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{
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if (((env->spr[SPR_970_HID5] >> 7) & 0x3) == 1) {
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do_dcbz(env, addr, 32);
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} else {
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do_dcbz(env, addr, env->dcache_line_size);
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#if !defined(CONFIG_USER_ONLY) && defined(TARGET_PPC64)
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if (!is_dcbzl &&
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(env->excp_model == POWERPC_EXCP_970) &&
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((env->spr[SPR_970_HID5] >> 7) & 0x3) == 1) {
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dcbz_size = 32;
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}
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#endif
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/* XXX add e500mc support */
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do_dcbz(env, addr, dcbz_size);
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}
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void helper_icbi(CPUPPCState *env, target_ulong addr)
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@ -4118,29 +4118,21 @@ static void gen_dcbtst(DisasContext *ctx)
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/* dcbz */
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static void gen_dcbz(DisasContext *ctx)
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{
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TCGv t0;
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gen_set_access_type(ctx, ACCESS_CACHE);
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/* NIP cannot be restored if the memory exception comes from an helper */
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gen_update_nip(ctx, ctx->nip - 4);
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t0 = tcg_temp_new();
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gen_addr_reg_index(ctx, t0);
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gen_helper_dcbz(cpu_env, t0);
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tcg_temp_free(t0);
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}
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TCGv tcgv_addr;
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TCGv_i32 tcgv_is_dcbzl;
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int is_dcbzl = ctx->opcode & 0x00200000 ? 1 : 0;
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static void gen_dcbz_970(DisasContext *ctx)
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{
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TCGv t0;
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gen_set_access_type(ctx, ACCESS_CACHE);
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/* NIP cannot be restored if the memory exception comes from an helper */
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gen_update_nip(ctx, ctx->nip - 4);
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t0 = tcg_temp_new();
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gen_addr_reg_index(ctx, t0);
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if (ctx->opcode & 0x00200000)
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gen_helper_dcbz(cpu_env, t0);
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else
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gen_helper_dcbz_970(cpu_env, t0);
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tcg_temp_free(t0);
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tcgv_addr = tcg_temp_new();
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tcgv_is_dcbzl = tcg_const_i32(is_dcbzl);
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gen_addr_reg_index(ctx, tcgv_addr);
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gen_helper_dcbz(cpu_env, tcgv_addr, tcgv_is_dcbzl);
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tcg_temp_free(tcgv_addr);
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tcg_temp_free_i32(tcgv_is_dcbzl);
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}
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/* dst / dstt */
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@ -8648,8 +8640,7 @@ GEN_HANDLER(dcbi, 0x1F, 0x16, 0x0E, 0x03E00001, PPC_CACHE),
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GEN_HANDLER(dcbst, 0x1F, 0x16, 0x01, 0x03E00001, PPC_CACHE),
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GEN_HANDLER(dcbt, 0x1F, 0x16, 0x08, 0x02000001, PPC_CACHE),
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GEN_HANDLER(dcbtst, 0x1F, 0x16, 0x07, 0x02000001, PPC_CACHE),
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GEN_HANDLER(dcbz, 0x1F, 0x16, 0x1F, 0x03E00001, PPC_CACHE_DCBZ),
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GEN_HANDLER2(dcbz_970, "dcbz", 0x1F, 0x16, 0x1F, 0x03C00001, PPC_CACHE_DCBZT),
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GEN_HANDLER(dcbz, 0x1F, 0x16, 0x1F, 0x03C00001, PPC_CACHE_DCBZ),
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GEN_HANDLER(dst, 0x1F, 0x16, 0x0A, 0x01800001, PPC_ALTIVEC),
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GEN_HANDLER(dstst, 0x1F, 0x16, 0x0B, 0x02000001, PPC_ALTIVEC),
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GEN_HANDLER(dss, 0x1F, 0x16, 0x19, 0x019FF801, PPC_ALTIVEC),
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@ -6298,7 +6298,7 @@ static void init_proc_7457 (CPUPPCState *env)
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PPC_FLOAT | PPC_FLOAT_FSEL | PPC_FLOAT_FRES | \
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PPC_FLOAT_FSQRT | PPC_FLOAT_FRSQRTE | \
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PPC_FLOAT_STFIWX | \
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PPC_CACHE | PPC_CACHE_ICBI | PPC_CACHE_DCBZT | \
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PPC_CACHE | PPC_CACHE_ICBI | PPC_CACHE_DCBZ | \
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PPC_MEM_SYNC | PPC_MEM_EIEIO | \
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PPC_MEM_TLBIE | PPC_MEM_TLBSYNC | \
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PPC_64B | PPC_ALTIVEC | \
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@ -6394,7 +6394,7 @@ static void init_proc_970 (CPUPPCState *env)
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PPC_FLOAT | PPC_FLOAT_FSEL | PPC_FLOAT_FRES | \
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PPC_FLOAT_FSQRT | PPC_FLOAT_FRSQRTE | \
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PPC_FLOAT_STFIWX | \
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PPC_CACHE | PPC_CACHE_ICBI | PPC_CACHE_DCBZT | \
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PPC_CACHE | PPC_CACHE_ICBI | PPC_CACHE_DCBZ | \
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PPC_MEM_SYNC | PPC_MEM_EIEIO | \
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PPC_MEM_TLBIE | PPC_MEM_TLBSYNC | \
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PPC_64B | PPC_ALTIVEC | \
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@ -6496,7 +6496,7 @@ static void init_proc_970FX (CPUPPCState *env)
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PPC_FLOAT | PPC_FLOAT_FSEL | PPC_FLOAT_FRES | \
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PPC_FLOAT_FSQRT | PPC_FLOAT_FRSQRTE | \
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PPC_FLOAT_STFIWX | \
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PPC_CACHE | PPC_CACHE_ICBI | PPC_CACHE_DCBZT | \
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PPC_CACHE | PPC_CACHE_ICBI | PPC_CACHE_DCBZ | \
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PPC_MEM_SYNC | PPC_MEM_EIEIO | \
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PPC_MEM_TLBIE | PPC_MEM_TLBSYNC | \
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PPC_64B | PPC_ALTIVEC | \
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@ -6586,7 +6586,7 @@ static void init_proc_970GX (CPUPPCState *env)
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PPC_FLOAT | PPC_FLOAT_FSEL | PPC_FLOAT_FRES | \
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PPC_FLOAT_FSQRT | PPC_FLOAT_FRSQRTE | \
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PPC_FLOAT_STFIWX | \
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PPC_CACHE | PPC_CACHE_ICBI | PPC_CACHE_DCBZT | \
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PPC_CACHE | PPC_CACHE_ICBI | PPC_CACHE_DCBZ | \
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PPC_MEM_SYNC | PPC_MEM_EIEIO | \
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PPC_MEM_TLBIE | PPC_MEM_TLBSYNC | \
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PPC_64B | PPC_ALTIVEC | \
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@ -6677,7 +6677,7 @@ static void init_proc_970MP (CPUPPCState *env)
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PPC_FLOAT | PPC_FLOAT_FSEL | PPC_FLOAT_FRES | \
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PPC_FLOAT_FSQRT | PPC_FLOAT_FRSQRTE | \
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PPC_FLOAT_STFIWX | \
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PPC_CACHE | PPC_CACHE_ICBI | PPC_CACHE_DCBZT | \
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PPC_CACHE | PPC_CACHE_ICBI | PPC_CACHE_DCBZ | \
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PPC_MEM_SYNC | PPC_MEM_EIEIO | \
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PPC_MEM_TLBIE | PPC_MEM_TLBSYNC | \
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PPC_64B | PPC_ALTIVEC | \
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