mirror of https://gitee.com/openkylin/qemu.git
target-ppc: add lxvb16x instruction
lxvb16x: Load VSX Vector Byte*16 Little/Big-endian Storage +--+--+--+--+--+--+--+--+--+--+--+--+--+--+--+--+ |F0|F1|F2|F3|F4|F5|F6|F7|E0|E1|E2|E3|E4|E5|E6|E7| +--+--+--+--+--+--+--+--+--+--+--+--+--+--+--+--+ Vector load results in (8-bit elements): +--+--+--+--+--+--+--+--+--+--+--+--+--+--+--+--+ |F0|F1|F2|F3|F4|F5|F6|F7|E0|E1|E2|E3|E4|E5|E6|E7| +--+--+--+--+--+--+--+--+--+--+--+--+--+--+--+--+ Signed-off-by: Nikunj A Dadhania <nikunj@linux.vnet.ibm.com> Reviewed-by: Richard Henderson <rth@twiddle.net> Signed-off-by: David Gibson <david@gibson.dropbear.id.au>
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@ -155,6 +155,25 @@ static void gen_lxvh8x(DisasContext *ctx)
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tcg_temp_free(EA);
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}
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static void gen_lxvb16x(DisasContext *ctx)
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{
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TCGv EA;
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TCGv_i64 xth = cpu_vsrh(xT(ctx->opcode));
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TCGv_i64 xtl = cpu_vsrl(xT(ctx->opcode));
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if (unlikely(!ctx->vsx_enabled)) {
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gen_exception(ctx, POWERPC_EXCP_VSXU);
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return;
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}
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gen_set_access_type(ctx, ACCESS_INT);
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EA = tcg_temp_new();
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gen_addr_reg_index(ctx, EA);
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tcg_gen_qemu_ld_i64(xth, EA, ctx->mem_idx, MO_BEQ);
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tcg_gen_addi_tl(EA, EA, 8);
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tcg_gen_qemu_ld_i64(xtl, EA, ctx->mem_idx, MO_BEQ);
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tcg_temp_free(EA);
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}
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#define VSX_STORE_SCALAR(name, operation) \
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static void gen_##name(DisasContext *ctx) \
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{ \
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@ -8,6 +8,7 @@ GEN_HANDLER_E(lxvd2x, 0x1F, 0x0C, 0x1A, 0, PPC_NONE, PPC2_VSX),
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GEN_HANDLER_E(lxvdsx, 0x1F, 0x0C, 0x0A, 0, PPC_NONE, PPC2_VSX),
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GEN_HANDLER_E(lxvw4x, 0x1F, 0x0C, 0x18, 0, PPC_NONE, PPC2_VSX),
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GEN_HANDLER_E(lxvh8x, 0x1F, 0x0C, 0x19, 0, PPC_NONE, PPC2_ISA300),
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GEN_HANDLER_E(lxvb16x, 0x1F, 0x0C, 0x1B, 0, PPC_NONE, PPC2_ISA300),
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GEN_HANDLER_E(stxsdx, 0x1F, 0xC, 0x16, 0, PPC_NONE, PPC2_VSX),
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GEN_HANDLER_E(stxsibx, 0x1F, 0xD, 0x1C, 0, PPC_NONE, PPC2_ISA300),
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