mirror of https://gitee.com/openkylin/qemu.git
ppc/pnv: Introduce PBA registers
The PBA bridge unit (Power Bus Access) connects the OCC (On Chip Controller) to the Power bus and System Memory. The PBA is used to gather sensor data, for power management, for sleep states, for initial boot, among other things. The PBA logic provides a set of four registers PowerBus Access Base Address Registers (PBABAR0..3) which map the OCC address space to the PowerBus space. These registers are setup by the initial FW and define the PowerBus Range of system memory that can be accessed by PBA. The current modeling of the PBABAR registers is done under the common XSCOM handlers. We introduce a specific XSCOM regions for these registers and fix : - BAR sizes and BAR masks - The mapping of the OCC common area. It is common to all chips and should be mapped once. We will address per-OCC area in the next change. - OCC common area is in BAR 3 on P8 Inspired by previous work of Balamuruhan S <bala24@linux.ibm.com> Signed-off-by: Cédric Le Goater <clg@kaod.org> Message-Id: <20191211082912.2625-2-clg@kaod.org> Signed-off-by: David Gibson <david@gibson.dropbear.id.au>
This commit is contained in:
Cédric Le Goater
David Gibson
parent
90cce00c7b
commit
8f09231631
12
hw/ppc/pnv.c
12
hw/ppc/pnv.c
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@ -1065,7 +1065,7 @@ static void pnv_chip_power8_realize(DeviceState *dev, Error **errp)
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pnv_xscom_add_subregion(chip, PNV_XSCOM_OCC_BASE, &chip8->occ.xscom_regs);
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/* OCC SRAM model */
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memory_region_add_subregion(get_system_memory(), PNV_OCC_COMMON_AREA(chip),
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memory_region_add_subregion(get_system_memory(), PNV_OCC_COMMON_AREA_BASE,
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&chip8->occ.sram_regs);
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/* HOMER */
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@ -1077,6 +1077,10 @@ static void pnv_chip_power8_realize(DeviceState *dev, Error **errp)
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error_propagate(errp, local_err);
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return;
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}
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/* Homer Xscom region */
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pnv_xscom_add_subregion(chip, PNV_XSCOM_PBA_BASE, &chip8->homer.pba_regs);
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/* Homer mmio region */
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memory_region_add_subregion(get_system_memory(), PNV_HOMER_BASE(chip),
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&chip8->homer.regs);
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}
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@ -1274,7 +1278,7 @@ static void pnv_chip_power9_realize(DeviceState *dev, Error **errp)
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pnv_xscom_add_subregion(chip, PNV9_XSCOM_OCC_BASE, &chip9->occ.xscom_regs);
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/* OCC SRAM model */
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memory_region_add_subregion(get_system_memory(), PNV9_OCC_COMMON_AREA(chip),
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memory_region_add_subregion(get_system_memory(), PNV9_OCC_COMMON_AREA_BASE,
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&chip9->occ.sram_regs);
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/* HOMER */
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@ -1286,6 +1290,10 @@ static void pnv_chip_power9_realize(DeviceState *dev, Error **errp)
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error_propagate(errp, local_err);
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return;
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}
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/* Homer Xscom region */
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pnv_xscom_add_subregion(chip, PNV9_XSCOM_PBA_BASE, &chip9->homer.pba_regs);
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/* Homer mmio region */
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memory_region_add_subregion(get_system_memory(), PNV9_HOMER_BASE(chip),
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&chip9->homer.regs);
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}
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@ -17,6 +17,7 @@
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*/
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#include "qemu/osdep.h"
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#include "qemu/log.h"
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#include "qapi/error.h"
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#include "exec/hwaddr.h"
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#include "exec/memory.h"
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@ -25,6 +26,7 @@
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#include "hw/qdev-properties.h"
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#include "hw/ppc/pnv.h"
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#include "hw/ppc/pnv_homer.h"
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#include "hw/ppc/pnv_xscom.h"
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static bool core_max_array(PnvHomer *homer, hwaddr addr)
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@ -114,10 +116,67 @@ static const MemoryRegionOps pnv_power8_homer_ops = {
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.endianness = DEVICE_BIG_ENDIAN,
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};
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/* P8 PBA BARs */
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#define PBA_BAR0 0x00
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#define PBA_BAR1 0x01
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#define PBA_BAR2 0x02
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#define PBA_BAR3 0x03
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#define PBA_BARMASK0 0x04
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#define PBA_BARMASK1 0x05
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#define PBA_BARMASK2 0x06
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#define PBA_BARMASK3 0x07
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static uint64_t pnv_homer_power8_pba_read(void *opaque, hwaddr addr,
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unsigned size)
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{
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PnvHomer *homer = PNV_HOMER(opaque);
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PnvChip *chip = homer->chip;
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uint32_t reg = addr >> 3;
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uint64_t val = 0;
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switch (reg) {
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case PBA_BAR0:
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val = PNV_HOMER_BASE(chip);
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break;
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case PBA_BARMASK0: /* P8 homer region mask */
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val = (PNV_HOMER_SIZE - 1) & 0x300000;
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break;
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case PBA_BAR3: /* P8 occ common area */
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val = PNV_OCC_COMMON_AREA_BASE;
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break;
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case PBA_BARMASK3: /* P8 occ common area mask */
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val = (PNV_OCC_COMMON_AREA_SIZE - 1) & 0x700000;
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break;
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default:
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qemu_log_mask(LOG_UNIMP, "PBA: read to unimplemented register: Ox%"
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HWADDR_PRIx "\n", addr >> 3);
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}
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return val;
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}
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static void pnv_homer_power8_pba_write(void *opaque, hwaddr addr,
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uint64_t val, unsigned size)
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{
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qemu_log_mask(LOG_UNIMP, "PBA: write to unimplemented register: Ox%"
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HWADDR_PRIx "\n", addr >> 3);
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}
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static const MemoryRegionOps pnv_homer_power8_pba_ops = {
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.read = pnv_homer_power8_pba_read,
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.write = pnv_homer_power8_pba_write,
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.valid.min_access_size = 8,
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.valid.max_access_size = 8,
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.impl.min_access_size = 8,
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.impl.max_access_size = 8,
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.endianness = DEVICE_BIG_ENDIAN,
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};
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static void pnv_homer_power8_class_init(ObjectClass *klass, void *data)
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{
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PnvHomerClass *homer = PNV_HOMER_CLASS(klass);
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homer->pba_size = PNV_XSCOM_PBA_SIZE;
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homer->pba_ops = &pnv_homer_power8_pba_ops;
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homer->homer_size = PNV_HOMER_SIZE;
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homer->homer_ops = &pnv_power8_homer_ops;
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homer->core_max_base = PNV8_CORE_MAX_BASE;
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@ -210,10 +269,57 @@ static const MemoryRegionOps pnv_power9_homer_ops = {
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.endianness = DEVICE_BIG_ENDIAN,
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};
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static uint64_t pnv_homer_power9_pba_read(void *opaque, hwaddr addr,
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unsigned size)
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{
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PnvHomer *homer = PNV_HOMER(opaque);
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PnvChip *chip = homer->chip;
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uint32_t reg = addr >> 3;
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uint64_t val = 0;
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switch (reg) {
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case PBA_BAR0:
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val = PNV9_HOMER_BASE(chip);
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break;
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case PBA_BARMASK0: /* P9 homer region mask */
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val = (PNV9_HOMER_SIZE - 1) & 0x300000;
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break;
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case PBA_BAR2: /* P9 occ common area */
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val = PNV9_OCC_COMMON_AREA_BASE;
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break;
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case PBA_BARMASK2: /* P9 occ common area size */
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val = (PNV9_OCC_COMMON_AREA_SIZE - 1) & 0x700000;
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break;
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default:
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qemu_log_mask(LOG_UNIMP, "PBA: read to unimplemented register: Ox%"
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HWADDR_PRIx "\n", addr >> 3);
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}
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return val;
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}
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static void pnv_homer_power9_pba_write(void *opaque, hwaddr addr,
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uint64_t val, unsigned size)
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{
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qemu_log_mask(LOG_UNIMP, "PBA: write to unimplemented register: Ox%"
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HWADDR_PRIx "\n", addr >> 3);
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}
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static const MemoryRegionOps pnv_homer_power9_pba_ops = {
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.read = pnv_homer_power9_pba_read,
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.write = pnv_homer_power9_pba_write,
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.valid.min_access_size = 8,
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.valid.max_access_size = 8,
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.impl.min_access_size = 8,
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.impl.max_access_size = 8,
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.endianness = DEVICE_BIG_ENDIAN,
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};
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static void pnv_homer_power9_class_init(ObjectClass *klass, void *data)
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{
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PnvHomerClass *homer = PNV_HOMER_CLASS(klass);
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homer->pba_size = PNV9_XSCOM_PBA_SIZE;
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homer->pba_ops = &pnv_homer_power9_pba_ops;
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homer->homer_size = PNV9_HOMER_SIZE;
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homer->homer_ops = &pnv_power9_homer_ops;
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homer->core_max_base = PNV9_CORE_MAX_BASE;
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@ -233,6 +339,9 @@ static void pnv_homer_realize(DeviceState *dev, Error **errp)
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assert(homer->chip);
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pnv_xscom_region_init(&homer->pba_regs, OBJECT(dev), hmrc->pba_ops,
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homer, "xscom-pba", hmrc->pba_size);
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/* homer region */
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memory_region_init_io(&homer->regs, OBJECT(dev),
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hmrc->homer_ops, homer, "homer-main-memory",
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@ -36,16 +36,6 @@
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#define PRD_P9_IPOLL_REG_MASK 0x000F0033
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#define PRD_P9_IPOLL_REG_STATUS 0x000F0034
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/* PBA BARs */
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#define P8_PBA_BAR0 0x2013f00
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#define P8_PBA_BAR2 0x2013f02
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#define P8_PBA_BARMASK0 0x2013f04
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#define P8_PBA_BARMASK2 0x2013f06
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#define P9_PBA_BAR0 0x5012b00
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#define P9_PBA_BAR2 0x5012b02
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#define P9_PBA_BARMASK0 0x5012b04
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#define P9_PBA_BARMASK2 0x5012b06
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static void xscom_complete(CPUState *cs, uint64_t hmer_bits)
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{
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/*
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@ -90,26 +80,6 @@ static uint64_t xscom_read_default(PnvChip *chip, uint32_t pcba)
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case 0x18002: /* ECID2 */
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return 0;
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case P9_PBA_BAR0:
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return PNV9_HOMER_BASE(chip);
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case P8_PBA_BAR0:
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return PNV_HOMER_BASE(chip);
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case P9_PBA_BARMASK0: /* P9 homer region size */
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return PNV9_HOMER_SIZE;
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case P8_PBA_BARMASK0: /* P8 homer region size */
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return PNV_HOMER_SIZE;
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case P9_PBA_BAR2: /* P9 occ common area */
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return PNV9_OCC_COMMON_AREA(chip);
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case P8_PBA_BAR2: /* P8 occ common area */
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return PNV_OCC_COMMON_AREA(chip);
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case P9_PBA_BARMASK2: /* P9 occ common area size */
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return PNV9_OCC_COMMON_AREA_SIZE;
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case P8_PBA_BARMASK2: /* P8 occ common area size */
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return PNV_OCC_COMMON_AREA_SIZE;
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case 0x1010c00: /* PIBAM FIR */
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case 0x1010c03: /* PIBAM FIR MASK */
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@ -130,9 +100,7 @@ static uint64_t xscom_read_default(PnvChip *chip, uint32_t pcba)
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case 0x202000f: /* ADU stuff, receive status register*/
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return 0;
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case 0x2013f01: /* PBA stuff */
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case 0x2013f03: /* PBA stuff */
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case 0x2013f05: /* PBA stuff */
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case 0x2013f07: /* PBA stuff */
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return 0;
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case 0x2013028: /* CAPP stuff */
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case 0x201302a: /* CAPP stuff */
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@ -244,12 +244,10 @@ IPMIBmc *pnv_bmc_create(void);
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#define PNV_XSCOM_BASE(chip) \
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(0x0003fc0000000000ull + ((uint64_t)(chip)->chip_id) * PNV_XSCOM_SIZE)
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#define PNV_OCC_COMMON_AREA_SIZE 0x0000000000700000ull
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#define PNV_OCC_COMMON_AREA(chip) \
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(0x7fff800000ull + ((uint64_t)PNV_CHIP_INDEX(chip) * \
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PNV_OCC_COMMON_AREA_SIZE))
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#define PNV_OCC_COMMON_AREA_SIZE 0x0000000000800000ull
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#define PNV_OCC_COMMON_AREA_BASE 0x7fff800000ull
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#define PNV_HOMER_SIZE 0x0000000000300000ull
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#define PNV_HOMER_SIZE 0x0000000000400000ull
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#define PNV_HOMER_BASE(chip) \
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(0x7ffd800000ull + ((uint64_t)PNV_CHIP_INDEX(chip)) * PNV_HOMER_SIZE)
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@ -312,12 +310,10 @@ IPMIBmc *pnv_bmc_create(void);
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#define PNV9_XSCOM_SIZE 0x0000000400000000ull
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#define PNV9_XSCOM_BASE(chip) PNV9_CHIP_BASE(chip, 0x00603fc00000000ull)
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#define PNV9_OCC_COMMON_AREA_SIZE 0x0000000000700000ull
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#define PNV9_OCC_COMMON_AREA(chip) \
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(0x203fff800000ull + ((uint64_t)PNV_CHIP_INDEX(chip) * \
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PNV9_OCC_COMMON_AREA_SIZE))
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#define PNV9_OCC_COMMON_AREA_SIZE 0x0000000000800000ull
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#define PNV9_OCC_COMMON_AREA_BASE 0x203fff800000ull
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#define PNV9_HOMER_SIZE 0x0000000000300000ull
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#define PNV9_HOMER_SIZE 0x0000000000400000ull
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#define PNV9_HOMER_BASE(chip) \
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(0x203ffd800000ull + ((uint64_t)PNV_CHIP_INDEX(chip)) * PNV9_HOMER_SIZE)
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@ -33,6 +33,7 @@ typedef struct PnvHomer {
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DeviceState parent;
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struct PnvChip *chip;
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MemoryRegion pba_regs;
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MemoryRegion regs;
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} PnvHomer;
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@ -44,6 +45,8 @@ typedef struct PnvHomer {
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typedef struct PnvHomerClass {
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DeviceClass parent_class;
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int pba_size;
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const MemoryRegionOps *pba_ops;
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int homer_size;
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const MemoryRegionOps *homer_ops;
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@ -68,6 +68,9 @@ typedef struct PnvXScomInterfaceClass {
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#define PNV_XSCOM_OCC_BASE 0x0066000
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#define PNV_XSCOM_OCC_SIZE 0x6000
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#define PNV_XSCOM_PBA_BASE 0x2013f00
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#define PNV_XSCOM_PBA_SIZE 0x40
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/*
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* Layout of the XSCOM PCB addresses (POWER 9)
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*/
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@ -82,6 +85,9 @@ typedef struct PnvXScomInterfaceClass {
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#define PNV9_XSCOM_OCC_BASE PNV_XSCOM_OCC_BASE
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#define PNV9_XSCOM_OCC_SIZE 0x8000
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#define PNV9_XSCOM_PBA_BASE 0x5012b00
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#define PNV9_XSCOM_PBA_SIZE 0x40
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#define PNV9_XSCOM_PSIHB_BASE 0x5012900
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#define PNV9_XSCOM_PSIHB_SIZE 0x100
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