mirror of https://gitee.com/openkylin/qemu.git
tcg-ppc: Fix and cleanup tcg_out_tlb_check
The fix is that sparc has so many mmu modes that the last one overflowed the 16-bit signed offset we assumed would fit. Handle this, and check the new assumption at compile time. Load the tlb addend earlier for the fast path. Remove the explicit address + addend and make use of index addressing. Adjust constraints for qemu_ld64 such that we don't clobber the address register or tlb addend before loading both values. Signed-off-by: Richard Henderson <rth@twiddle.net>
This commit is contained in:
Richard Henderson
parent
5b1c985b7e
commit
8f50c841b3
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@ -575,42 +575,72 @@ static const void * const qemu_st_helpers[4] = {
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static void *ld_trampolines[4];
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static void *st_trampolines[4];
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static void tcg_out_tlb_check (TCGContext *s, int r0, int r1, int r2,
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int addr_reg, int addr_reg2, int s_bits,
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int offset1, int offset2, uint8_t **label_ptr)
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/* Perform the TLB load and compare. Branches to the slow path, placing the
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address of the branch in *LABEL_PTR. Loads the addend of the TLB into R0.
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Clobbers R1 and R2. */
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static void tcg_out_tlb_check(TCGContext *s, TCGReg r0, TCGReg r1, TCGReg r2,
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TCGReg addrlo, TCGReg addrhi, int s_bits,
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int mem_index, int is_load, uint8_t **label_ptr)
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{
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int cmp_off =
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(is_load
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? offsetof(CPUArchState, tlb_table[mem_index][0].addr_read)
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: offsetof(CPUArchState, tlb_table[mem_index][0].addr_write));
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int add_off = offsetof(CPUArchState, tlb_table[mem_index][0].addend);
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uint16_t retranst;
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TCGReg base = TCG_AREG0;
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tcg_out32 (s, (RLWINM
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| RA (r0)
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| RS (addr_reg)
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| SH (32 - (TARGET_PAGE_BITS - CPU_TLB_ENTRY_BITS))
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| MB (32 - (CPU_TLB_BITS + CPU_TLB_ENTRY_BITS))
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| ME (31 - CPU_TLB_ENTRY_BITS)
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)
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);
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tcg_out32 (s, ADD | RT (r0) | RA (r0) | RB (TCG_AREG0));
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tcg_out32 (s, (LWZU
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| RT (r1)
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| RA (r0)
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| offset1
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)
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);
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tcg_out32 (s, (RLWINM
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| RA (r2)
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| RS (addr_reg)
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| SH (0)
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| MB ((32 - s_bits) & 31)
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| ME (31 - TARGET_PAGE_BITS)
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)
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);
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/* Extract the page index, shifted into place for tlb index. */
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tcg_out32(s, (RLWINM
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| RA(r0)
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| RS(addrlo)
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| SH(32 - (TARGET_PAGE_BITS - CPU_TLB_ENTRY_BITS))
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| MB(32 - (CPU_TLB_BITS + CPU_TLB_ENTRY_BITS))
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| ME(31 - CPU_TLB_ENTRY_BITS)));
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tcg_out32 (s, CMP | BF (7) | RA (r2) | RB (r1));
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#if TARGET_LONG_BITS == 64
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tcg_out32 (s, LWZ | RT (r1) | RA (r0) | 4);
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tcg_out32 (s, CMP | BF (6) | RA (addr_reg2) | RB (r1));
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tcg_out32 (s, CRAND | BT (7, CR_EQ) | BA (6, CR_EQ) | BB (7, CR_EQ));
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#endif
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/* Compensate for very large offsets. */
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if (add_off >= 0x8000) {
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/* Most target env are smaller than 32k; none are larger than 64k.
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Simplify the logic here merely to offset by 0x7ff0, giving us a
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range just shy of 64k. Check this assumption. */
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QEMU_BUILD_BUG_ON(offsetof(CPUArchState,
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tlb_table[NB_MMU_MODES - 1][1])
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> 0x7ff0 + 0x7fff);
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tcg_out32(s, ADDI | RT(r1) | RA(base) | 0x7ff0);
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base = r1;
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cmp_off -= 0x7ff0;
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add_off -= 0x7ff0;
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}
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/* Clear the non-page, non-alignment bits from the address. */
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tcg_out32(s, (RLWINM
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| RA(r2)
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| RS(addrlo)
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| SH(0)
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| MB((32 - s_bits) & 31)
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| ME(31 - TARGET_PAGE_BITS)));
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tcg_out32(s, ADD | RT(r0) | RA(r0) | RB(base));
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base = r0;
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/* Load the tlb comparator. */
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tcg_out32(s, LWZ | RT(r1) | RA(base) | (cmp_off & 0xffff));
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tcg_out32(s, CMP | BF(7) | RA(r2) | RB(r1));
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if (TARGET_LONG_BITS == 64) {
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tcg_out32(s, LWZ | RT(r1) | RA(base) | ((cmp_off + 4) & 0xffff));
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}
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/* Load the tlb addend for use on the fast path.
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Do this asap to minimize load delay. */
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tcg_out32(s, LWZ | RT(r0) | RA(base) | (add_off & 0xffff));
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if (TARGET_LONG_BITS == 64) {
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tcg_out32(s, CMP | BF(6) | RA(addrhi) | RB(r1));
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tcg_out32(s, CRAND | BT(7, CR_EQ) | BA(6, CR_EQ) | BB(7, CR_EQ));
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}
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/* Use a conditional branch-and-link so that we load a pointer to
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somewhere within the current opcode, for passing on to the helper.
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@ -619,58 +649,31 @@ static void tcg_out_tlb_check (TCGContext *s, int r0, int r1, int r2,
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*label_ptr = s->code_ptr;
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retranst = ((uint16_t *) s->code_ptr)[1] & ~3;
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tcg_out32(s, BC | BI(7, CR_EQ) | retranst | BO_COND_FALSE | LK);
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/* r0 now contains &env->tlb_table[mem_index][index].addr_x */
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tcg_out32 (s, (LWZ
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| RT (r0)
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| RA (r0)
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| offset2
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)
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);
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/* r0 = env->tlb_table[mem_index][index].addend */
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tcg_out32 (s, ADD | RT (r0) | RA (r0) | RB (addr_reg));
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/* r0 = env->tlb_table[mem_index][index].addend + addr */
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}
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#endif
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static void tcg_out_qemu_ld (TCGContext *s, const TCGArg *args, int opc)
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{
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int addr_reg, data_reg, data_reg2, r0, r1, rbase, bswap;
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TCGReg addrlo, datalo, datahi, rbase;
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int bswap;
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#ifdef CONFIG_SOFTMMU
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int mem_index, s_bits, r2, addr_reg2;
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int mem_index;
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TCGReg addrhi;
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uint8_t *label_ptr;
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#endif
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data_reg = *args++;
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if (opc == 3)
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data_reg2 = *args++;
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else
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data_reg2 = 0;
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addr_reg = *args++;
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datalo = *args++;
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datahi = (opc == 3 ? *args++ : 0);
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addrlo = *args++;
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#ifdef CONFIG_SOFTMMU
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#if TARGET_LONG_BITS == 64
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addr_reg2 = *args++;
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#else
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addr_reg2 = 0;
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#endif
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addrhi = (TARGET_LONG_BITS == 64 ? *args++ : 0);
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mem_index = *args;
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s_bits = opc & 3;
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r0 = 3;
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r1 = 4;
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r2 = 0;
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rbase = 0;
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tcg_out_tlb_check (
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s, r0, r1, r2, addr_reg, addr_reg2, s_bits,
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offsetof (CPUArchState, tlb_table[mem_index][0].addr_read),
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offsetof (CPUTLBEntry, addend) - offsetof (CPUTLBEntry, addr_read),
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&label_ptr
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);
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tcg_out_tlb_check(s, TCG_REG_R3, TCG_REG_R4, TCG_REG_R0, addrlo,
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addrhi, opc & 3, mem_index, 0, &label_ptr);
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rbase = TCG_REG_R3;
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#else /* !CONFIG_SOFTMMU */
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r0 = addr_reg;
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r1 = 3;
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rbase = GUEST_BASE ? TCG_GUEST_BASE_REG : 0;
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#endif
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@ -683,106 +686,72 @@ static void tcg_out_qemu_ld (TCGContext *s, const TCGArg *args, int opc)
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switch (opc) {
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default:
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case 0:
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tcg_out32 (s, LBZX | TAB (data_reg, rbase, r0));
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tcg_out32(s, LBZX | TAB(datalo, rbase, addrlo));
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break;
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case 0|4:
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tcg_out32 (s, LBZX | TAB (data_reg, rbase, r0));
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tcg_out32 (s, EXTSB | RA (data_reg) | RS (data_reg));
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tcg_out32(s, LBZX | TAB(datalo, rbase, addrlo));
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tcg_out32(s, EXTSB | RA(datalo) | RS(datalo));
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break;
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case 1:
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if (bswap)
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tcg_out32 (s, LHBRX | TAB (data_reg, rbase, r0));
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else
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tcg_out32 (s, LHZX | TAB (data_reg, rbase, r0));
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tcg_out32(s, (bswap ? LHBRX : LHZX) | TAB(datalo, rbase, addrlo));
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break;
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case 1|4:
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if (bswap) {
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tcg_out32 (s, LHBRX | TAB (data_reg, rbase, r0));
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tcg_out32 (s, EXTSH | RA (data_reg) | RS (data_reg));
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tcg_out32(s, LHBRX | TAB(datalo, rbase, addrlo));
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tcg_out32(s, EXTSH | RA(datalo) | RS(datalo));
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} else {
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tcg_out32(s, LHAX | TAB(datalo, rbase, addrlo));
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}
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else tcg_out32 (s, LHAX | TAB (data_reg, rbase, r0));
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break;
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case 2:
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if (bswap)
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tcg_out32 (s, LWBRX | TAB (data_reg, rbase, r0));
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else
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tcg_out32 (s, LWZX | TAB (data_reg, rbase, r0));
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tcg_out32(s, (bswap ? LWBRX : LWZX) | TAB(datalo, rbase, addrlo));
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break;
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case 3:
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if (bswap) {
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tcg_out32 (s, ADDI | RT (r1) | RA (r0) | 4);
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tcg_out32 (s, LWBRX | TAB (data_reg, rbase, r0));
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tcg_out32 (s, LWBRX | TAB (data_reg2, rbase, r1));
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}
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else {
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#ifdef CONFIG_USE_GUEST_BASE
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tcg_out32 (s, ADDI | RT (r1) | RA (r0) | 4);
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tcg_out32 (s, LWZX | TAB (data_reg2, rbase, r0));
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tcg_out32 (s, LWZX | TAB (data_reg, rbase, r1));
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#else
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if (r0 == data_reg2) {
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tcg_out32 (s, LWZ | RT (0) | RA (r0));
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tcg_out32 (s, LWZ | RT (data_reg) | RA (r0) | 4);
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tcg_out_mov (s, TCG_TYPE_I32, data_reg2, 0);
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}
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else {
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tcg_out32 (s, LWZ | RT (data_reg2) | RA (r0));
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tcg_out32 (s, LWZ | RT (data_reg) | RA (r0) | 4);
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}
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#endif
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tcg_out32(s, ADDI | RT(TCG_REG_R0) | RA(addrlo) | 4);
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tcg_out32(s, LWBRX | TAB(datalo, rbase, addrlo));
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tcg_out32(s, LWBRX | TAB(datahi, rbase, TCG_REG_R0));
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} else if (rbase != 0) {
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tcg_out32(s, ADDI | RT(TCG_REG_R0) | RA(addrlo) | 4);
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tcg_out32(s, LWZX | TAB(datahi, rbase, addrlo));
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tcg_out32(s, LWZX | TAB(datalo, rbase, TCG_REG_R0));
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} else if (addrlo == datahi) {
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tcg_out32(s, LWZ | RT(datalo) | RA(addrlo) | 4);
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tcg_out32(s, LWZ | RT(datahi) | RA(addrlo));
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} else {
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tcg_out32(s, LWZ | RT(datahi) | RA(addrlo));
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tcg_out32(s, LWZ | RT(datalo) | RA(addrlo) | 4);
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}
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break;
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}
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#ifdef CONFIG_SOFTMMU
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add_qemu_ldst_label (s,
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1,
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opc,
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data_reg,
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data_reg2,
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addr_reg,
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addr_reg2,
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mem_index,
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s->code_ptr,
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label_ptr);
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add_qemu_ldst_label(s, 1, opc, datalo, datahi, addrlo,
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addrhi, mem_index, s->code_ptr, label_ptr);
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#endif
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}
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static void tcg_out_qemu_st (TCGContext *s, const TCGArg *args, int opc)
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{
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int addr_reg, r0, r1, data_reg, data_reg2, bswap, rbase;
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TCGReg addrlo, datalo, datahi, rbase;
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int bswap;
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#ifdef CONFIG_SOFTMMU
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int mem_index, r2, addr_reg2;
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int mem_index;
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TCGReg addrhi;
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uint8_t *label_ptr;
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#endif
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data_reg = *args++;
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if (opc == 3)
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data_reg2 = *args++;
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else
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data_reg2 = 0;
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addr_reg = *args++;
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datalo = *args++;
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datahi = (opc == 3 ? *args++ : 0);
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addrlo = *args++;
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#ifdef CONFIG_SOFTMMU
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#if TARGET_LONG_BITS == 64
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addr_reg2 = *args++;
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#else
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addr_reg2 = 0;
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#endif
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addrhi = (TARGET_LONG_BITS == 64 ? *args++ : 0);
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mem_index = *args;
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r0 = 3;
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r1 = 4;
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r2 = 0;
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rbase = 0;
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tcg_out_tlb_check (
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s, r0, r1, r2, addr_reg, addr_reg2, opc & 3,
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offsetof (CPUArchState, tlb_table[mem_index][0].addr_write),
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offsetof (CPUTLBEntry, addend) - offsetof (CPUTLBEntry, addr_write),
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&label_ptr
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);
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tcg_out_tlb_check(s, TCG_REG_R3, TCG_REG_R4, TCG_REG_R0, addrlo,
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addrhi, opc & 3, mem_index, 0, &label_ptr);
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rbase = TCG_REG_R3;
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#else /* !CONFIG_SOFTMMU */
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r0 = addr_reg;
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r1 = 3;
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rbase = GUEST_BASE ? TCG_GUEST_BASE_REG : 0;
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#endif
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@ -793,50 +762,33 @@ static void tcg_out_qemu_st (TCGContext *s, const TCGArg *args, int opc)
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#endif
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switch (opc) {
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case 0:
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tcg_out32 (s, STBX | SAB (data_reg, rbase, r0));
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tcg_out32(s, STBX | SAB(datalo, rbase, addrlo));
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break;
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case 1:
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if (bswap)
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tcg_out32 (s, STHBRX | SAB (data_reg, rbase, r0));
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else
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tcg_out32 (s, STHX | SAB (data_reg, rbase, r0));
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tcg_out32(s, (bswap ? STHBRX : STHX) | SAB(datalo, rbase, addrlo));
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break;
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case 2:
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if (bswap)
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tcg_out32 (s, STWBRX | SAB (data_reg, rbase, r0));
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else
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tcg_out32 (s, STWX | SAB (data_reg, rbase, r0));
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tcg_out32(s, (bswap ? STWBRX : STWX) | SAB(datalo, rbase, addrlo));
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break;
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case 3:
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if (bswap) {
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tcg_out32 (s, ADDI | RT (r1) | RA (r0) | 4);
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tcg_out32 (s, STWBRX | SAB (data_reg, rbase, r0));
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tcg_out32 (s, STWBRX | SAB (data_reg2, rbase, r1));
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}
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else {
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#ifdef CONFIG_USE_GUEST_BASE
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tcg_out32 (s, STWX | SAB (data_reg2, rbase, r0));
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tcg_out32 (s, ADDI | RT (r1) | RA (r0) | 4);
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tcg_out32 (s, STWX | SAB (data_reg, rbase, r1));
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#else
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tcg_out32 (s, STW | RS (data_reg2) | RA (r0));
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tcg_out32 (s, STW | RS (data_reg) | RA (r0) | 4);
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#endif
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tcg_out32(s, ADDI | RT(TCG_REG_R0) | RA(addrlo) | 4);
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tcg_out32(s, STWBRX | SAB(datalo, rbase, addrlo));
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tcg_out32(s, STWBRX | SAB(datahi, rbase, TCG_REG_R0));
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} else if (rbase != 0) {
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tcg_out32(s, ADDI | RT(TCG_REG_R0) | RA(addrlo) | 4);
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tcg_out32(s, STWX | SAB(datahi, rbase, addrlo));
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tcg_out32(s, STWX | SAB(datalo, rbase, TCG_REG_R0));
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} else {
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tcg_out32(s, STW | RS(datahi) | RA(addrlo));
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tcg_out32(s, STW | RS(datalo) | RA(addrlo) | 4);
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}
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break;
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}
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#ifdef CONFIG_SOFTMMU
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add_qemu_ldst_label (s,
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0,
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opc,
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data_reg,
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data_reg2,
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addr_reg,
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addr_reg2,
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mem_index,
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s->code_ptr,
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label_ptr);
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add_qemu_ldst_label(s, 0, opc, datalo, datahi, addrlo, addrhi,
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mem_index, s->code_ptr, label_ptr);
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#endif
|
||||
}
|
||||
|
||||
|
|
@ -1994,7 +1946,7 @@ static const TCGTargetOpDef ppc_op_defs[] = {
|
|||
{ INDEX_op_qemu_ld16u, { "r", "L" } },
|
||||
{ INDEX_op_qemu_ld16s, { "r", "L" } },
|
||||
{ INDEX_op_qemu_ld32, { "r", "L" } },
|
||||
{ INDEX_op_qemu_ld64, { "r", "r", "L" } },
|
||||
{ INDEX_op_qemu_ld64, { "L", "L", "L" } },
|
||||
|
||||
{ INDEX_op_qemu_st8, { "K", "K" } },
|
||||
{ INDEX_op_qemu_st16, { "K", "K" } },
|
||||
|
|
@ -2006,7 +1958,7 @@ static const TCGTargetOpDef ppc_op_defs[] = {
|
|||
{ INDEX_op_qemu_ld16u, { "r", "L", "L" } },
|
||||
{ INDEX_op_qemu_ld16s, { "r", "L", "L" } },
|
||||
{ INDEX_op_qemu_ld32, { "r", "L", "L" } },
|
||||
{ INDEX_op_qemu_ld64, { "r", "L", "L", "L" } },
|
||||
{ INDEX_op_qemu_ld64, { "L", "L", "L", "L" } },
|
||||
|
||||
{ INDEX_op_qemu_st8, { "K", "K", "K" } },
|
||||
{ INDEX_op_qemu_st16, { "K", "K", "K" } },
|
||||
|
|
|
|||
Loading…
Reference in New Issue