mirror of https://gitee.com/openkylin/qemu.git
linux-user: move tilegx cpu loop to tilegx directory
No code change, only move code from main.c to tilegx/cpu_loop.c. Signed-off-by: Laurent Vivier <laurent@vivier.eu> Reviewed-by: Richard Henderson <richard.henderson@linaro.org> Message-Id: <20180411185651.21351-17-laurent@vivier.eu>
This commit is contained in:
Laurent Vivier
parent
a5fd8ee1f7
commit
9397e56497
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@ -149,262 +149,6 @@ void fork_end(int child)
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}
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}
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#ifdef TARGET_TILEGX
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static void gen_sigill_reg(CPUTLGState *env)
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{
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target_siginfo_t info;
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info.si_signo = TARGET_SIGILL;
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info.si_errno = 0;
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info.si_code = TARGET_ILL_PRVREG;
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info._sifields._sigfault._addr = env->pc;
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queue_signal(env, info.si_signo, QEMU_SI_FAULT, &info);
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}
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static void do_signal(CPUTLGState *env, int signo, int sigcode)
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{
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target_siginfo_t info;
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info.si_signo = signo;
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info.si_errno = 0;
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info._sifields._sigfault._addr = env->pc;
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if (signo == TARGET_SIGSEGV) {
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/* The passed in sigcode is a dummy; check for a page mapping
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and pass either MAPERR or ACCERR. */
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target_ulong addr = env->excaddr;
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info._sifields._sigfault._addr = addr;
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if (page_check_range(addr, 1, PAGE_VALID) < 0) {
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sigcode = TARGET_SEGV_MAPERR;
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} else {
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sigcode = TARGET_SEGV_ACCERR;
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}
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}
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info.si_code = sigcode;
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queue_signal(env, info.si_signo, QEMU_SI_FAULT, &info);
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}
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static void gen_sigsegv_maperr(CPUTLGState *env, target_ulong addr)
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{
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env->excaddr = addr;
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do_signal(env, TARGET_SIGSEGV, 0);
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}
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static void set_regval(CPUTLGState *env, uint8_t reg, uint64_t val)
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{
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if (unlikely(reg >= TILEGX_R_COUNT)) {
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switch (reg) {
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case TILEGX_R_SN:
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case TILEGX_R_ZERO:
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return;
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case TILEGX_R_IDN0:
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case TILEGX_R_IDN1:
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case TILEGX_R_UDN0:
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case TILEGX_R_UDN1:
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case TILEGX_R_UDN2:
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case TILEGX_R_UDN3:
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gen_sigill_reg(env);
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return;
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default:
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g_assert_not_reached();
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}
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}
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env->regs[reg] = val;
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}
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/*
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* Compare the 8-byte contents of the CmpValue SPR with the 8-byte value in
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* memory at the address held in the first source register. If the values are
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* not equal, then no memory operation is performed. If the values are equal,
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* the 8-byte quantity from the second source register is written into memory
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* at the address held in the first source register. In either case, the result
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* of the instruction is the value read from memory. The compare and write to
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* memory are atomic and thus can be used for synchronization purposes. This
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* instruction only operates for addresses aligned to a 8-byte boundary.
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* Unaligned memory access causes an Unaligned Data Reference interrupt.
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*
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* Functional Description (64-bit)
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* uint64_t memVal = memoryReadDoubleWord (rf[SrcA]);
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* rf[Dest] = memVal;
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* if (memVal == SPR[CmpValueSPR])
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* memoryWriteDoubleWord (rf[SrcA], rf[SrcB]);
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*
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* Functional Description (32-bit)
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* uint64_t memVal = signExtend32 (memoryReadWord (rf[SrcA]));
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* rf[Dest] = memVal;
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* if (memVal == signExtend32 (SPR[CmpValueSPR]))
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* memoryWriteWord (rf[SrcA], rf[SrcB]);
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*
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*
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* This function also processes exch and exch4 which need not process SPR.
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*/
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static void do_exch(CPUTLGState *env, bool quad, bool cmp)
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{
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target_ulong addr;
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target_long val, sprval;
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start_exclusive();
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addr = env->atomic_srca;
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if (quad ? get_user_s64(val, addr) : get_user_s32(val, addr)) {
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goto sigsegv_maperr;
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}
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if (cmp) {
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if (quad) {
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sprval = env->spregs[TILEGX_SPR_CMPEXCH];
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} else {
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sprval = sextract64(env->spregs[TILEGX_SPR_CMPEXCH], 0, 32);
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}
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}
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if (!cmp || val == sprval) {
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target_long valb = env->atomic_srcb;
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if (quad ? put_user_u64(valb, addr) : put_user_u32(valb, addr)) {
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goto sigsegv_maperr;
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}
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}
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set_regval(env, env->atomic_dstr, val);
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end_exclusive();
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return;
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sigsegv_maperr:
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end_exclusive();
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gen_sigsegv_maperr(env, addr);
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}
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static void do_fetch(CPUTLGState *env, int trapnr, bool quad)
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{
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int8_t write = 1;
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target_ulong addr;
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target_long val, valb;
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start_exclusive();
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addr = env->atomic_srca;
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valb = env->atomic_srcb;
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if (quad ? get_user_s64(val, addr) : get_user_s32(val, addr)) {
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goto sigsegv_maperr;
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}
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switch (trapnr) {
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case TILEGX_EXCP_OPCODE_FETCHADD:
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case TILEGX_EXCP_OPCODE_FETCHADD4:
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valb += val;
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break;
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case TILEGX_EXCP_OPCODE_FETCHADDGEZ:
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valb += val;
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if (valb < 0) {
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write = 0;
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}
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break;
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case TILEGX_EXCP_OPCODE_FETCHADDGEZ4:
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valb += val;
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if ((int32_t)valb < 0) {
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write = 0;
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}
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break;
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case TILEGX_EXCP_OPCODE_FETCHAND:
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case TILEGX_EXCP_OPCODE_FETCHAND4:
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valb &= val;
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break;
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case TILEGX_EXCP_OPCODE_FETCHOR:
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case TILEGX_EXCP_OPCODE_FETCHOR4:
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valb |= val;
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break;
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default:
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g_assert_not_reached();
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}
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if (write) {
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if (quad ? put_user_u64(valb, addr) : put_user_u32(valb, addr)) {
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goto sigsegv_maperr;
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}
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}
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set_regval(env, env->atomic_dstr, val);
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end_exclusive();
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return;
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sigsegv_maperr:
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end_exclusive();
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gen_sigsegv_maperr(env, addr);
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}
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void cpu_loop(CPUTLGState *env)
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{
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CPUState *cs = CPU(tilegx_env_get_cpu(env));
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int trapnr;
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while (1) {
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cpu_exec_start(cs);
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trapnr = cpu_exec(cs);
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cpu_exec_end(cs);
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process_queued_cpu_work(cs);
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switch (trapnr) {
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case TILEGX_EXCP_SYSCALL:
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{
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abi_ulong ret = do_syscall(env, env->regs[TILEGX_R_NR],
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env->regs[0], env->regs[1],
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env->regs[2], env->regs[3],
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env->regs[4], env->regs[5],
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env->regs[6], env->regs[7]);
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if (ret == -TARGET_ERESTARTSYS) {
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env->pc -= 8;
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} else if (ret != -TARGET_QEMU_ESIGRETURN) {
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env->regs[TILEGX_R_RE] = ret;
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env->regs[TILEGX_R_ERR] = TILEGX_IS_ERRNO(ret) ? -ret : 0;
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}
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break;
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}
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case TILEGX_EXCP_OPCODE_EXCH:
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do_exch(env, true, false);
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break;
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case TILEGX_EXCP_OPCODE_EXCH4:
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do_exch(env, false, false);
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break;
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case TILEGX_EXCP_OPCODE_CMPEXCH:
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do_exch(env, true, true);
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break;
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case TILEGX_EXCP_OPCODE_CMPEXCH4:
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do_exch(env, false, true);
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break;
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case TILEGX_EXCP_OPCODE_FETCHADD:
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case TILEGX_EXCP_OPCODE_FETCHADDGEZ:
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case TILEGX_EXCP_OPCODE_FETCHAND:
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case TILEGX_EXCP_OPCODE_FETCHOR:
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do_fetch(env, trapnr, true);
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break;
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case TILEGX_EXCP_OPCODE_FETCHADD4:
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case TILEGX_EXCP_OPCODE_FETCHADDGEZ4:
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case TILEGX_EXCP_OPCODE_FETCHAND4:
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case TILEGX_EXCP_OPCODE_FETCHOR4:
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do_fetch(env, trapnr, false);
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break;
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case TILEGX_EXCP_SIGNAL:
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do_signal(env, env->signo, env->sigcode);
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break;
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case TILEGX_EXCP_REG_IDN_ACCESS:
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case TILEGX_EXCP_REG_UDN_ACCESS:
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gen_sigill_reg(env);
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break;
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case EXCP_ATOMIC:
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cpu_exec_step_atomic(cs);
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break;
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default:
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fprintf(stderr, "trapnr is %d[0x%x].\n", trapnr, trapnr);
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g_assert_not_reached();
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}
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process_pending_signals(env);
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}
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}
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#endif
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#ifdef TARGET_RISCV
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void cpu_loop(CPURISCVState *env)
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@ -1583,17 +1327,6 @@ int main(int argc, char **argv, char **envp)
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env->pc = regs->sepc;
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env->gpr[xSP] = regs->sp;
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}
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#elif defined(TARGET_TILEGX)
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{
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int i;
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for (i = 0; i < TILEGX_R_COUNT; i++) {
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env->regs[i] = regs->regs[i];
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}
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for (i = 0; i < TILEGX_SPR_COUNT; i++) {
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env->spregs[i] = 0;
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}
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env->pc = regs->pc;
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}
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#elif defined(TARGET_HPPA)
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{
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int i;
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@ -21,6 +21,266 @@
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#include "qemu.h"
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#include "cpu_loop-common.h"
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static void gen_sigill_reg(CPUTLGState *env)
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{
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target_siginfo_t info;
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info.si_signo = TARGET_SIGILL;
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info.si_errno = 0;
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info.si_code = TARGET_ILL_PRVREG;
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info._sifields._sigfault._addr = env->pc;
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queue_signal(env, info.si_signo, QEMU_SI_FAULT, &info);
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}
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static void do_signal(CPUTLGState *env, int signo, int sigcode)
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{
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target_siginfo_t info;
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info.si_signo = signo;
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info.si_errno = 0;
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info._sifields._sigfault._addr = env->pc;
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if (signo == TARGET_SIGSEGV) {
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/* The passed in sigcode is a dummy; check for a page mapping
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and pass either MAPERR or ACCERR. */
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target_ulong addr = env->excaddr;
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info._sifields._sigfault._addr = addr;
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if (page_check_range(addr, 1, PAGE_VALID) < 0) {
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sigcode = TARGET_SEGV_MAPERR;
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} else {
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sigcode = TARGET_SEGV_ACCERR;
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}
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}
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info.si_code = sigcode;
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queue_signal(env, info.si_signo, QEMU_SI_FAULT, &info);
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}
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static void gen_sigsegv_maperr(CPUTLGState *env, target_ulong addr)
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{
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env->excaddr = addr;
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do_signal(env, TARGET_SIGSEGV, 0);
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}
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static void set_regval(CPUTLGState *env, uint8_t reg, uint64_t val)
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{
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if (unlikely(reg >= TILEGX_R_COUNT)) {
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switch (reg) {
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case TILEGX_R_SN:
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case TILEGX_R_ZERO:
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return;
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case TILEGX_R_IDN0:
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case TILEGX_R_IDN1:
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case TILEGX_R_UDN0:
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case TILEGX_R_UDN1:
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case TILEGX_R_UDN2:
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case TILEGX_R_UDN3:
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gen_sigill_reg(env);
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return;
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default:
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g_assert_not_reached();
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}
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}
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env->regs[reg] = val;
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}
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/*
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* Compare the 8-byte contents of the CmpValue SPR with the 8-byte value in
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* memory at the address held in the first source register. If the values are
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* not equal, then no memory operation is performed. If the values are equal,
|
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* the 8-byte quantity from the second source register is written into memory
|
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* at the address held in the first source register. In either case, the result
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* of the instruction is the value read from memory. The compare and write to
|
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* memory are atomic and thus can be used for synchronization purposes. This
|
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* instruction only operates for addresses aligned to a 8-byte boundary.
|
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* Unaligned memory access causes an Unaligned Data Reference interrupt.
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*
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* Functional Description (64-bit)
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* uint64_t memVal = memoryReadDoubleWord (rf[SrcA]);
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* rf[Dest] = memVal;
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* if (memVal == SPR[CmpValueSPR])
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* memoryWriteDoubleWord (rf[SrcA], rf[SrcB]);
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*
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* Functional Description (32-bit)
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* uint64_t memVal = signExtend32 (memoryReadWord (rf[SrcA]));
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* rf[Dest] = memVal;
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* if (memVal == signExtend32 (SPR[CmpValueSPR]))
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* memoryWriteWord (rf[SrcA], rf[SrcB]);
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*
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*
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* This function also processes exch and exch4 which need not process SPR.
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*/
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static void do_exch(CPUTLGState *env, bool quad, bool cmp)
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{
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target_ulong addr;
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target_long val, sprval;
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start_exclusive();
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addr = env->atomic_srca;
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if (quad ? get_user_s64(val, addr) : get_user_s32(val, addr)) {
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goto sigsegv_maperr;
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}
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if (cmp) {
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if (quad) {
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sprval = env->spregs[TILEGX_SPR_CMPEXCH];
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} else {
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sprval = sextract64(env->spregs[TILEGX_SPR_CMPEXCH], 0, 32);
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}
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}
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if (!cmp || val == sprval) {
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target_long valb = env->atomic_srcb;
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if (quad ? put_user_u64(valb, addr) : put_user_u32(valb, addr)) {
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goto sigsegv_maperr;
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}
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}
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set_regval(env, env->atomic_dstr, val);
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end_exclusive();
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return;
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sigsegv_maperr:
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end_exclusive();
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gen_sigsegv_maperr(env, addr);
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}
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static void do_fetch(CPUTLGState *env, int trapnr, bool quad)
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{
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int8_t write = 1;
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target_ulong addr;
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target_long val, valb;
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|
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start_exclusive();
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addr = env->atomic_srca;
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valb = env->atomic_srcb;
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if (quad ? get_user_s64(val, addr) : get_user_s32(val, addr)) {
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goto sigsegv_maperr;
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}
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switch (trapnr) {
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case TILEGX_EXCP_OPCODE_FETCHADD:
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case TILEGX_EXCP_OPCODE_FETCHADD4:
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valb += val;
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break;
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case TILEGX_EXCP_OPCODE_FETCHADDGEZ:
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valb += val;
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if (valb < 0) {
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write = 0;
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}
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break;
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case TILEGX_EXCP_OPCODE_FETCHADDGEZ4:
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valb += val;
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if ((int32_t)valb < 0) {
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write = 0;
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}
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break;
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case TILEGX_EXCP_OPCODE_FETCHAND:
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case TILEGX_EXCP_OPCODE_FETCHAND4:
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valb &= val;
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break;
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case TILEGX_EXCP_OPCODE_FETCHOR:
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case TILEGX_EXCP_OPCODE_FETCHOR4:
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valb |= val;
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break;
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default:
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g_assert_not_reached();
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}
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if (write) {
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if (quad ? put_user_u64(valb, addr) : put_user_u32(valb, addr)) {
|
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goto sigsegv_maperr;
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}
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}
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set_regval(env, env->atomic_dstr, val);
|
||||
end_exclusive();
|
||||
return;
|
||||
|
||||
sigsegv_maperr:
|
||||
end_exclusive();
|
||||
gen_sigsegv_maperr(env, addr);
|
||||
}
|
||||
|
||||
void cpu_loop(CPUTLGState *env)
|
||||
{
|
||||
CPUState *cs = CPU(tilegx_env_get_cpu(env));
|
||||
int trapnr;
|
||||
|
||||
while (1) {
|
||||
cpu_exec_start(cs);
|
||||
trapnr = cpu_exec(cs);
|
||||
cpu_exec_end(cs);
|
||||
process_queued_cpu_work(cs);
|
||||
|
||||
switch (trapnr) {
|
||||
case TILEGX_EXCP_SYSCALL:
|
||||
{
|
||||
abi_ulong ret = do_syscall(env, env->regs[TILEGX_R_NR],
|
||||
env->regs[0], env->regs[1],
|
||||
env->regs[2], env->regs[3],
|
||||
env->regs[4], env->regs[5],
|
||||
env->regs[6], env->regs[7]);
|
||||
if (ret == -TARGET_ERESTARTSYS) {
|
||||
env->pc -= 8;
|
||||
} else if (ret != -TARGET_QEMU_ESIGRETURN) {
|
||||
env->regs[TILEGX_R_RE] = ret;
|
||||
env->regs[TILEGX_R_ERR] = TILEGX_IS_ERRNO(ret) ? -ret : 0;
|
||||
}
|
||||
break;
|
||||
}
|
||||
case TILEGX_EXCP_OPCODE_EXCH:
|
||||
do_exch(env, true, false);
|
||||
break;
|
||||
case TILEGX_EXCP_OPCODE_EXCH4:
|
||||
do_exch(env, false, false);
|
||||
break;
|
||||
case TILEGX_EXCP_OPCODE_CMPEXCH:
|
||||
do_exch(env, true, true);
|
||||
break;
|
||||
case TILEGX_EXCP_OPCODE_CMPEXCH4:
|
||||
do_exch(env, false, true);
|
||||
break;
|
||||
case TILEGX_EXCP_OPCODE_FETCHADD:
|
||||
case TILEGX_EXCP_OPCODE_FETCHADDGEZ:
|
||||
case TILEGX_EXCP_OPCODE_FETCHAND:
|
||||
case TILEGX_EXCP_OPCODE_FETCHOR:
|
||||
do_fetch(env, trapnr, true);
|
||||
break;
|
||||
case TILEGX_EXCP_OPCODE_FETCHADD4:
|
||||
case TILEGX_EXCP_OPCODE_FETCHADDGEZ4:
|
||||
case TILEGX_EXCP_OPCODE_FETCHAND4:
|
||||
case TILEGX_EXCP_OPCODE_FETCHOR4:
|
||||
do_fetch(env, trapnr, false);
|
||||
break;
|
||||
case TILEGX_EXCP_SIGNAL:
|
||||
do_signal(env, env->signo, env->sigcode);
|
||||
break;
|
||||
case TILEGX_EXCP_REG_IDN_ACCESS:
|
||||
case TILEGX_EXCP_REG_UDN_ACCESS:
|
||||
gen_sigill_reg(env);
|
||||
break;
|
||||
case EXCP_ATOMIC:
|
||||
cpu_exec_step_atomic(cs);
|
||||
break;
|
||||
default:
|
||||
fprintf(stderr, "trapnr is %d[0x%x].\n", trapnr, trapnr);
|
||||
g_assert_not_reached();
|
||||
}
|
||||
process_pending_signals(env);
|
||||
}
|
||||
}
|
||||
|
||||
void target_cpu_copy_regs(CPUArchState *env, struct target_pt_regs *regs)
|
||||
{
|
||||
int i;
|
||||
for (i = 0; i < TILEGX_R_COUNT; i++) {
|
||||
env->regs[i] = regs->regs[i];
|
||||
}
|
||||
for (i = 0; i < TILEGX_SPR_COUNT; i++) {
|
||||
env->spregs[i] = 0;
|
||||
}
|
||||
env->pc = regs->pc;
|
||||
}
|
||||
|
|
|
|||
Loading…
Reference in New Issue