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ARM: fix smmul and smmla/smmls usage of registers (Mans Rullgard). 

This fixes the destination and accumulator registers for the smmul
and smmla instructions.

Signed-off-by: Mans Rullgard <mans@mansr.com>
Acked-by: Laurent Desnogues <laurent.desnogues@gmail.com>
Signed-off-by: Andrzej Zaborowski <andrew.zaborowski@intel.com>


git-svn-id: svn://svn.savannah.nongnu.org/qemu/trunk@5913 c046a42c-6fe2-441c-8c8c-71466251a162
This commit is contained in:
balrog 2008-12-07 14:18:02 +00:00
parent ded9d29547
commit 955a7dd5e8
1 changed files with 3 additions and 3 deletions
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6
target-arm/translate.c
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@ -6507,8 +6507,8 @@ static void disas_arm_insn(CPUState * env, DisasContext *s)
tcg_gen_shri_i64(tmp64, tmp64, 32); tcg_gen_shri_i64(tmp64, tmp64, 32);
tmp = new_tmp(); tmp = new_tmp();
tcg_gen_trunc_i64_i32(tmp, tmp64); tcg_gen_trunc_i64_i32(tmp, tmp64);
if (rn != 15) { if (rd != 15) {
tmp2 = load_reg(s, rn); tmp2 = load_reg(s, rd);
if (insn & (1 << 6)) { if (insn & (1 << 6)) {
tcg_gen_sub_i32(tmp, tmp, tmp2); tcg_gen_sub_i32(tmp, tmp, tmp2);
} else { } else {
@ -6516,7 +6516,7 @@ static void disas_arm_insn(CPUState * env, DisasContext *s)
} }
dead_tmp(tmp2); dead_tmp(tmp2);
} }
store_reg(s, rd, tmp); store_reg(s, rn, tmp);
} else { } else {
if (insn & (1 << 5)) if (insn & (1 << 5))
gen_swap_half(tmp2); gen_swap_half(tmp2);