From 9843a0d2c62d683c1940cfd2d7c6533837b56bb2 Mon Sep 17 00:00:00 2001
From: ths <ths@c046a42c-6fe2-441c-8c8c-71466251a162>
Date: Wed, 11 Jun 2008 10:40:33 +0000
Subject: [PATCH] Free some more temporaries.

git-svn-id: svn://svn.savannah.nongnu.org/qemu/trunk@4729 c046a42c-6fe2-441c-8c8c-71466251a162
---
 target-mips/translate.c | 25 ++++++++++---------------
 1 file changed, 10 insertions(+), 15 deletions(-)

diff --git a/target-mips/translate.c b/target-mips/translate.c
index 7c54982d0b..2f6679b68b 100644
--- a/target-mips/translate.c
+++ b/target-mips/translate.c
@@ -840,21 +840,15 @@ static inline void gen_op_addr_add (void)
        See the MIPS64 PRA manual, section 4.10. */
     {
         int l1 = gen_new_label();
+        TCGv r_tmp = tcg_temp_local_new(TCG_TYPE_I32);
 
-        {
-            TCGv r_tmp = tcg_temp_new(TCG_TYPE_I32);
-
-            tcg_gen_ld_i32(r_tmp, cpu_env, offsetof(CPUState, hflags));
-            tcg_gen_andi_i32(r_tmp, r_tmp, MIPS_HFLAG_KSU);
-            tcg_gen_brcondi_i32(TCG_COND_NE, r_tmp, MIPS_HFLAG_UM, l1);
-        }
-        {
-            TCGv r_tmp = tcg_temp_new(TCG_TYPE_I32);
-
-            tcg_gen_ld_i32(r_tmp, cpu_env, offsetof(CPUState, CP0_Status));
-            tcg_gen_andi_i32(r_tmp, r_tmp, (1 << CP0St_UX));
-            tcg_gen_brcondi_i32(TCG_COND_NE, r_tmp, 0, l1);
-        }
+        tcg_gen_ld_i32(r_tmp, cpu_env, offsetof(CPUState, hflags));
+        tcg_gen_andi_i32(r_tmp, r_tmp, MIPS_HFLAG_KSU);
+        tcg_gen_brcondi_i32(TCG_COND_NE, r_tmp, MIPS_HFLAG_UM, l1);
+        tcg_gen_ld_i32(r_tmp, cpu_env, offsetof(CPUState, CP0_Status));
+        tcg_gen_andi_i32(r_tmp, r_tmp, (1 << CP0St_UX));
+        tcg_gen_brcondi_i32(TCG_COND_NE, r_tmp, 0, l1);
+        tcg_temp_free(r_tmp);
         tcg_gen_ext32s_i64(cpu_T[0], cpu_T[0]);
         gen_set_label(l1);
     }
@@ -5542,13 +5536,14 @@ static void gen_movci (DisasContext *ctx, int rd, int rs, int cc, int tf)
     gen_load_gpr(cpu_T[1], rs);
     {
         TCGv r_ptr = tcg_temp_new(TCG_TYPE_PTR);
-        TCGv r_tmp = tcg_temp_new(TCG_TYPE_I32);
+        TCGv r_tmp = tcg_temp_local_new(TCG_TYPE_I32);
 
         tcg_gen_ld_ptr(r_ptr, cpu_env, offsetof(CPUState, fpu));
         tcg_gen_ld_i32(r_tmp, r_ptr, offsetof(CPUMIPSFPUContext, fcr31));
         tcg_temp_free(r_ptr);
         tcg_gen_andi_i32(r_tmp, r_tmp, ccbit);
         tcg_gen_brcondi_i32(cond, r_tmp, 0, l1);
+        tcg_temp_free(r_tmp);
     }
     tcg_gen_mov_tl(cpu_T[0], cpu_T[1]);