mirror of https://gitee.com/openkylin/qemu.git
cputlb: move CPU_LOOP() for tlb_reset() to exec.c
To prepare for multi-arch, cputlb.c should only have awareness of one single architecture. This means it should not have access to the full CPU lists which may be heterogeneous. Instead, push the CPU_LOOP() up to the one and only caller in exec.c. Signed-off-by: Peter Crosthwaite <crosthwaite.peter@gmail.com> Message-Id: <db06dc6c49f8970caaf116d0385f00ee10a56f2f.1441614289.git.crosthwaite.peter@gmail.com> Signed-off-by: Paolo Bonzini <pbonzini@redhat.com>
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parent
5f12a788c0
commit
9a13565d52
27
cputlb.c
27
cputlb.c
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@ -262,27 +262,24 @@ static inline ram_addr_t qemu_ram_addr_from_host_nofail(void *ptr)
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return ram_addr;
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return ram_addr;
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}
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}
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void cpu_tlb_reset_dirty_all(ram_addr_t start1, ram_addr_t length)
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void tlb_reset_dirty(CPUState *cpu, ram_addr_t start1, ram_addr_t length)
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{
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{
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CPUState *cpu;
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CPUArchState *env;
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CPUArchState *env;
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CPU_FOREACH(cpu) {
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int mmu_idx;
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int mmu_idx;
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env = cpu->env_ptr;
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env = cpu->env_ptr;
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for (mmu_idx = 0; mmu_idx < NB_MMU_MODES; mmu_idx++) {
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for (mmu_idx = 0; mmu_idx < NB_MMU_MODES; mmu_idx++) {
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unsigned int i;
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unsigned int i;
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for (i = 0; i < CPU_TLB_SIZE; i++) {
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for (i = 0; i < CPU_TLB_SIZE; i++) {
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tlb_reset_dirty_range(&env->tlb_table[mmu_idx][i],
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tlb_reset_dirty_range(&env->tlb_table[mmu_idx][i],
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start1, length);
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start1, length);
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}
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}
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for (i = 0; i < CPU_VTLB_SIZE; i++) {
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for (i = 0; i < CPU_VTLB_SIZE; i++) {
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tlb_reset_dirty_range(&env->tlb_v_table[mmu_idx][i],
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tlb_reset_dirty_range(&env->tlb_v_table[mmu_idx][i],
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start1, length);
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start1, length);
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}
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}
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}
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}
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}
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}
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}
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5
exec.c
5
exec.c
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@ -913,6 +913,7 @@ found:
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static void tlb_reset_dirty_range_all(ram_addr_t start, ram_addr_t length)
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static void tlb_reset_dirty_range_all(ram_addr_t start, ram_addr_t length)
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{
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{
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CPUState *cpu;
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ram_addr_t start1;
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ram_addr_t start1;
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RAMBlock *block;
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RAMBlock *block;
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ram_addr_t end;
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ram_addr_t end;
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@ -924,7 +925,9 @@ static void tlb_reset_dirty_range_all(ram_addr_t start, ram_addr_t length)
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block = qemu_get_ram_block(start);
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block = qemu_get_ram_block(start);
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assert(block == qemu_get_ram_block(end - 1));
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assert(block == qemu_get_ram_block(end - 1));
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start1 = (uintptr_t)ramblock_ptr(block, start - block->offset);
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start1 = (uintptr_t)ramblock_ptr(block, start - block->offset);
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cpu_tlb_reset_dirty_all(start1, length);
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CPU_FOREACH(cpu) {
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tlb_reset_dirty(cpu, start1, length);
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}
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rcu_read_unlock();
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rcu_read_unlock();
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}
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}
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@ -25,7 +25,7 @@ void tlb_protect_code(ram_addr_t ram_addr);
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void tlb_unprotect_code(ram_addr_t ram_addr);
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void tlb_unprotect_code(ram_addr_t ram_addr);
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void tlb_reset_dirty_range(CPUTLBEntry *tlb_entry, uintptr_t start,
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void tlb_reset_dirty_range(CPUTLBEntry *tlb_entry, uintptr_t start,
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uintptr_t length);
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uintptr_t length);
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void cpu_tlb_reset_dirty_all(ram_addr_t start1, ram_addr_t length);
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void tlb_reset_dirty(CPUState *cpu, ram_addr_t start1, ram_addr_t length);
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void tlb_set_dirty(CPUArchState *env, target_ulong vaddr);
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void tlb_set_dirty(CPUArchState *env, target_ulong vaddr);
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extern int tlb_flush_count;
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extern int tlb_flush_count;
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