From 9ce89a22aed41e8486dddb27fbeea9f182b90516 Mon Sep 17 00:00:00 2001 From: =?UTF-8?q?Philippe=20Mathieu-Daud=C3=A9?= <f4bug@amsat.org> Date: Mon, 12 Oct 2020 14:49:54 +0200 Subject: [PATCH] hw/ssi: Update coding style to make checkpatch.pl happy MIME-Version: 1.0 Content-Type: text/plain; charset=UTF-8 Content-Transfer-Encoding: 8bit To make the next commit easier to review, clean this code first. Signed-off-by: Philippe Mathieu-Daudé <f4bug@amsat.org> Message-Id: <20201012124955.3409127-3-f4bug@amsat.org> Signed-off-by: Paolo Bonzini <pbonzini@redhat.com> --- include/hw/ssi/ssi.h | 16 +++++++++------- 1 file changed, 9 insertions(+), 7 deletions(-) diff --git a/include/hw/ssi/ssi.h b/include/hw/ssi/ssi.h index fe3028c39d..c15548425a 100644 --- a/include/hw/ssi/ssi.h +++ b/include/hw/ssi/ssi.h @@ -1,12 +1,14 @@ /* QEMU Synchronous Serial Interface support. */ -/* In principle SSI is a point-point interface. As such the qemu - implementation has a single slave device on a "bus". - However it is fairly common for boards to have multiple slaves - connected to a single master, and select devices with an external - chip select. This is implemented in qemu by having an explicit mux device. - It is assumed that master and slave are both using the same transfer width. - */ +/* + * In principle SSI is a point-point interface. As such the qemu + * implementation has a single slave device on a "bus". + * However it is fairly common for boards to have multiple slaves + * connected to a single master, and select devices with an external + * chip select. This is implemented in qemu by having an explicit mux device. + * It is assumed that master and slave are both using the same transfer + * width. + */ #ifndef QEMU_SSI_H #define QEMU_SSI_H