mirror of https://gitee.com/openkylin/qemu.git
Fix for PowerPC 64 rotates.
Fix for PowerPC 64 load & store with immediate index. git-svn-id: svn://svn.savannah.nongnu.org/qemu/trunk@2617 c046a42c-6fe2-441c-8c8c-71466251a162
This commit is contained in:
j_mayer
parent
74aa042996
commit
9d53c7535f
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@ -1264,8 +1264,8 @@ static inline void gen_rldicl (DisasContext *ctx, int mbn, int shn)
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{
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uint32_t sh, mb;
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sh = SH(ctx->opcode) | (1 << shn);
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mb = (MB(ctx->opcode) << 1) | mbn;
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sh = SH(ctx->opcode) | (shn << 5);
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mb = MB(ctx->opcode) | (mbn << 5);
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gen_rldinm(ctx, mb, 63, sh);
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}
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GEN_PPC64_R4(rldicl, 0x1E, 0x00);
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@ -1274,8 +1274,8 @@ static inline void gen_rldicr (DisasContext *ctx, int men, int shn)
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{
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uint32_t sh, me;
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sh = SH(ctx->opcode) | (1 << shn);
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me = (MB(ctx->opcode) << 1) | men;
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sh = SH(ctx->opcode) | (shn << 5);
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me = MB(ctx->opcode) | (men << 5);
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gen_rldinm(ctx, 0, me, sh);
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}
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GEN_PPC64_R4(rldicr, 0x1E, 0x02);
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@ -1284,8 +1284,8 @@ static inline void gen_rldic (DisasContext *ctx, int mbn, int shn)
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{
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uint32_t sh, mb;
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sh = SH(ctx->opcode) | (1 << shn);
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mb = (MB(ctx->opcode) << 1) | mbn;
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sh = SH(ctx->opcode) | (shn << 5);
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mb = MB(ctx->opcode) | (mbn << 5);
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gen_rldinm(ctx, mb, 63 - sh, sh);
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}
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GEN_PPC64_R4(rldic, 0x1E, 0x04);
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@ -1308,7 +1308,7 @@ static inline void gen_rldcl (DisasContext *ctx, int mbn)
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{
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uint32_t mb;
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mb = (MB(ctx->opcode) << 1) | mbn;
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mb = MB(ctx->opcode) | (mbn << 5);
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gen_rldnm(ctx, mb, 63);
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}
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GEN_PPC64_R2(rldcl, 0x1E, 0x08)
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@ -1317,7 +1317,7 @@ static inline void gen_rldcr (DisasContext *ctx, int men)
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{
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uint32_t me;
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me = (MB(ctx->opcode) << 1) | men;
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me = MB(ctx->opcode) | (men << 5);
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gen_rldnm(ctx, 0, me);
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}
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GEN_PPC64_R2(rldcr, 0x1E, 0x09)
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@ -1327,8 +1327,8 @@ static inline void gen_rldimi (DisasContext *ctx, int mbn, int shn)
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uint64_t mask;
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uint32_t sh, mb;
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sh = SH(ctx->opcode) | (1 << shn);
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mb = (MB(ctx->opcode) << 1) | mbn;
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sh = SH(ctx->opcode) | (shn << 5);
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mb = MB(ctx->opcode) | (mbn << 5);
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if (likely(sh == 0)) {
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if (likely(mb == 0)) {
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gen_op_load_gpr_T0(rS(ctx->opcode));
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@ -1732,10 +1732,12 @@ GEN_HANDLER(mtfsfi, 0x3F, 0x06, 0x04, 0x006f0800, PPC_FLOAT)
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/*** Addressing modes ***/
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/* Register indirect with immediate index : EA = (rA|0) + SIMM */
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static inline void gen_addr_imm_index (DisasContext *ctx)
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static inline void gen_addr_imm_index (DisasContext *ctx, int maskl)
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{
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target_long simm = SIMM(ctx->opcode);
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if (maskl)
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simm &= ~0x03;
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if (rA(ctx->opcode) == 0) {
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gen_set_T0(simm);
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} else {
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@ -1856,7 +1858,7 @@ static GenOpFunc *gen_op_st##width[] = { \
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#define GEN_LD(width, opc, type) \
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GEN_HANDLER(l##width, opc, 0xFF, 0xFF, 0x00000000, type) \
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{ \
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gen_addr_imm_index(ctx); \
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gen_addr_imm_index(ctx, 0); \
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op_ldst(l##width); \
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gen_op_store_T1_gpr(rD(ctx->opcode)); \
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}
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@ -1869,7 +1871,10 @@ GEN_HANDLER(l##width##u, opc, 0xFF, 0xFF, 0x00000000, type) \
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RET_INVAL(ctx); \
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return; \
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} \
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gen_addr_imm_index(ctx); \
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if (type == PPC_64B) \
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gen_addr_imm_index(ctx, 1); \
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else \
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gen_addr_imm_index(ctx, 0); \
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op_ldst(l##width); \
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gen_op_store_T1_gpr(rD(ctx->opcode)); \
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gen_op_store_T0_gpr(rA(ctx->opcode)); \
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@ -1932,7 +1937,7 @@ GEN_HANDLER(ld, 0x3A, 0xFF, 0xFF, 0x00000000, PPC_64B)
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return;
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}
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}
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gen_addr_imm_index(ctx);
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gen_addr_imm_index(ctx, 1);
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if (ctx->opcode & 0x02) {
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/* lwa (lwau is undefined) */
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op_ldst(lwa);
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@ -1950,7 +1955,7 @@ GEN_HANDLER(ld, 0x3A, 0xFF, 0xFF, 0x00000000, PPC_64B)
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#define GEN_ST(width, opc, type) \
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GEN_HANDLER(st##width, opc, 0xFF, 0xFF, 0x00000000, type) \
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{ \
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gen_addr_imm_index(ctx); \
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gen_addr_imm_index(ctx, 0); \
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gen_op_load_gpr_T1(rS(ctx->opcode)); \
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op_ldst(st##width); \
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}
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@ -1962,7 +1967,10 @@ GEN_HANDLER(st##width##u, opc, 0xFF, 0xFF, 0x00000000, type) \
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RET_INVAL(ctx); \
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return; \
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} \
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gen_addr_imm_index(ctx); \
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if (type == PPC_64B) \
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gen_addr_imm_index(ctx, 1); \
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else \
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gen_addr_imm_index(ctx, 0); \
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gen_op_load_gpr_T1(rS(ctx->opcode)); \
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op_ldst(st##width); \
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gen_op_store_T0_gpr(rA(ctx->opcode)); \
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@ -2014,7 +2022,7 @@ GEN_HANDLER(std, 0x3E, 0xFF, 0xFF, 0x00000002, PPC_64B)
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return;
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}
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}
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gen_addr_imm_index(ctx);
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gen_addr_imm_index(ctx, 1);
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gen_op_load_gpr_T1(rS(ctx->opcode));
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op_ldst(std);
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if (Rc(ctx->opcode))
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@ -2102,7 +2110,7 @@ GEN_HANDLER(lmw, 0x2E, 0xFF, 0xFF, 0x00000000, PPC_INTEGER)
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{
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/* NIP cannot be restored if the memory exception comes from an helper */
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gen_update_nip(ctx, ctx->nip - 4);
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gen_addr_imm_index(ctx);
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gen_addr_imm_index(ctx, 0);
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op_ldstm(lmw, rD(ctx->opcode));
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}
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@ -2111,7 +2119,7 @@ GEN_HANDLER(stmw, 0x2F, 0xFF, 0xFF, 0x00000000, PPC_INTEGER)
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{
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/* NIP cannot be restored if the memory exception comes from an helper */
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gen_update_nip(ctx, ctx->nip - 4);
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gen_addr_imm_index(ctx);
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gen_addr_imm_index(ctx, 0);
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op_ldstm(stmw, rS(ctx->opcode));
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}
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@ -2435,7 +2443,7 @@ GEN_HANDLER(l##width, opc, 0xFF, 0xFF, 0x00000000, PPC_FLOAT) \
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RET_EXCP(ctx, EXCP_NO_FP, 0); \
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return; \
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} \
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gen_addr_imm_index(ctx); \
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gen_addr_imm_index(ctx, 0); \
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op_ldst(l##width); \
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gen_op_store_FT0_fpr(rD(ctx->opcode)); \
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}
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@ -2451,7 +2459,7 @@ GEN_HANDLER(l##width##u, opc, 0xFF, 0xFF, 0x00000000, PPC_FLOAT) \
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RET_INVAL(ctx); \
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return; \
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} \
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gen_addr_imm_index(ctx); \
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gen_addr_imm_index(ctx, 0); \
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op_ldst(l##width); \
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gen_op_store_FT0_fpr(rD(ctx->opcode)); \
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gen_op_store_T0_gpr(rA(ctx->opcode)); \
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@ -2506,7 +2514,7 @@ GEN_HANDLER(st##width, opc, 0xFF, 0xFF, 0x00000000, PPC_FLOAT) \
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RET_EXCP(ctx, EXCP_NO_FP, 0); \
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return; \
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} \
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gen_addr_imm_index(ctx); \
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gen_addr_imm_index(ctx, 0); \
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gen_op_load_fpr_FT0(rS(ctx->opcode)); \
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op_ldst(st##width); \
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}
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@ -2522,7 +2530,7 @@ GEN_HANDLER(st##width##u, opc, 0xFF, 0xFF, 0x00000000, PPC_FLOAT) \
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RET_INVAL(ctx); \
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return; \
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} \
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gen_addr_imm_index(ctx); \
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gen_addr_imm_index(ctx, 0); \
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gen_op_load_fpr_FT0(rS(ctx->opcode)); \
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op_ldst(st##width); \
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gen_op_store_T0_gpr(rA(ctx->opcode)); \
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@ -4102,7 +4110,7 @@ GEN_HANDLER(lfq, 0x38, 0xFF, 0xFF, 0x00000003, PPC_POWER2)
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{
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/* NIP cannot be restored if the memory exception comes from an helper */
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gen_update_nip(ctx, ctx->nip - 4);
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gen_addr_imm_index(ctx);
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gen_addr_imm_index(ctx, 0);
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op_POWER2_lfq();
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gen_op_store_FT0_fpr(rD(ctx->opcode));
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gen_op_store_FT1_fpr(rD(ctx->opcode) + 1);
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@ -4115,7 +4123,7 @@ GEN_HANDLER(lfqu, 0x39, 0xFF, 0xFF, 0x00000003, PPC_POWER2)
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/* NIP cannot be restored if the memory exception comes from an helper */
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gen_update_nip(ctx, ctx->nip - 4);
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gen_addr_imm_index(ctx);
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gen_addr_imm_index(ctx, 0);
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op_POWER2_lfq();
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gen_op_store_FT0_fpr(rD(ctx->opcode));
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gen_op_store_FT1_fpr(rD(ctx->opcode) + 1);
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@ -4154,7 +4162,7 @@ GEN_HANDLER(stfq, 0x3C, 0xFF, 0xFF, 0x00000003, PPC_POWER2)
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{
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/* NIP cannot be restored if the memory exception comes from an helper */
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gen_update_nip(ctx, ctx->nip - 4);
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gen_addr_imm_index(ctx);
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gen_addr_imm_index(ctx, 0);
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gen_op_load_fpr_FT0(rS(ctx->opcode));
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gen_op_load_fpr_FT1(rS(ctx->opcode) + 1);
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op_POWER2_stfq();
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@ -4167,7 +4175,7 @@ GEN_HANDLER(stfqu, 0x3D, 0xFF, 0xFF, 0x00000003, PPC_POWER2)
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/* NIP cannot be restored if the memory exception comes from an helper */
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gen_update_nip(ctx, ctx->nip - 4);
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gen_addr_imm_index(ctx);
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gen_addr_imm_index(ctx, 0);
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gen_op_load_fpr_FT0(rS(ctx->opcode));
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gen_op_load_fpr_FT1(rS(ctx->opcode) + 1);
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op_POWER2_stfq();
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