mirror of https://gitee.com/openkylin/qemu.git
target/microblaze: Convert dec_msr to decodetree
Tested-by: Edgar E. Iglesias <edgar.iglesias@xilinx.com> Reviewed-by: Edgar E. Iglesias <edgar.iglesias@xilinx.com> Signed-off-by: Richard Henderson <richard.henderson@linaro.org>
This commit is contained in:
Richard Henderson
parent
536e340f46
commit
9df297a2d8
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@ -182,6 +182,9 @@ lwi 111010 ..... ..... ................ @typeb
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mbar 101110 imm:5 00010 0000 0000 0000 0100
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mfs 100101 rd:5 0 e:1 000 10 rs:14
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mts 100101 0 e:1 000 ra:5 11 rs:14
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msrclr 100101 ..... 100010 ............... @type_msr
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msrset 100101 ..... 100000 ............... @type_msr
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@ -1300,6 +1300,7 @@ static void msr_read(DisasContext *dc, TCGv_i32 d)
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tcg_temp_free_i32(t);
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}
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#ifndef CONFIG_USER_ONLY
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static void msr_write(DisasContext *dc, TCGv_i32 v)
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{
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dc->cpustate_changed = 1;
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@ -1310,6 +1311,7 @@ static void msr_write(DisasContext *dc, TCGv_i32 v)
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/* Clear MSR_C and MSR_CC; MSR_PVR is not writable, and is always clear. */
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tcg_gen_andi_i32(cpu_msr, v, ~(MSR_C | MSR_CC | MSR_PVR));
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}
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#endif
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static bool do_msrclrset(DisasContext *dc, arg_type_msr *arg, bool set)
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{
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@ -1358,151 +1360,152 @@ static bool trans_msrset(DisasContext *dc, arg_type_msr *arg)
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return do_msrclrset(dc, arg, true);
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}
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static void dec_msr(DisasContext *dc)
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static bool trans_mts(DisasContext *dc, arg_mts *arg)
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{
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CPUState *cs = CPU(dc->cpu);
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unsigned int sr, rn;
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bool to, extended = false;
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sr = extract32(dc->imm, 0, 14);
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to = extract32(dc->imm, 14, 1);
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dc->type_b = 1;
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if (to) {
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dc->cpustate_changed = 1;
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if (trap_userspace(dc, true)) {
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return true;
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}
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/* Extended MSRs are only available if addr_size > 32. */
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if (dc->cpu->cfg.addr_size > 32) {
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/* The E-bit is encoded differently for To/From MSR. */
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static const unsigned int e_bit[] = { 19, 24 };
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extended = extract32(dc->imm, e_bit[to], 1);
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#ifdef CONFIG_USER_ONLY
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g_assert_not_reached();
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#else
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if (arg->e && arg->rs != 0x1003) {
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qemu_log_mask(LOG_GUEST_ERROR,
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"Invalid extended mts reg 0x%x\n", arg->rs);
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return true;
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}
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if (trap_userspace(dc, to)) {
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return;
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}
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#if !defined(CONFIG_USER_ONLY)
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/* Catch read/writes to the mmu block. */
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if ((sr & ~0xff) == 0x1000) {
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TCGv_i32 tmp_ext = tcg_const_i32(extended);
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TCGv_i32 tmp_sr;
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sr &= 7;
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tmp_sr = tcg_const_i32(sr);
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if (to) {
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gen_helper_mmu_write(cpu_env, tmp_ext, tmp_sr, cpu_R[dc->ra]);
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} else {
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gen_helper_mmu_read(cpu_R[dc->rd], cpu_env, tmp_ext, tmp_sr);
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}
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tcg_temp_free_i32(tmp_sr);
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tcg_temp_free_i32(tmp_ext);
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return;
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}
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#endif
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if (to) {
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switch (sr) {
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case SR_PC:
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break;
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TCGv_i32 src = reg_for_read(dc, arg->ra);
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switch (arg->rs) {
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case SR_MSR:
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msr_write(dc, cpu_R[dc->ra]);
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msr_write(dc, src);
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break;
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case SR_FSR:
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tcg_gen_st_i32(src, cpu_env, offsetof(CPUMBState, fsr));
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break;
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case 0x800:
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tcg_gen_st_i32(src, cpu_env, offsetof(CPUMBState, slr));
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break;
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case 0x802:
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tcg_gen_st_i32(src, cpu_env, offsetof(CPUMBState, shr));
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break;
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case 0x1000: /* PID */
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case 0x1001: /* ZPR */
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case 0x1002: /* TLBX */
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case 0x1003: /* TLBLO */
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case 0x1004: /* TLBHI */
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case 0x1005: /* TLBSX */
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{
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TCGv_i32 tmp_ext = tcg_const_i32(arg->e);
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TCGv_i32 tmp_reg = tcg_const_i32(arg->rs & 7);
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gen_helper_mmu_write(cpu_env, tmp_ext, tmp_reg, src);
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tcg_temp_free_i32(tmp_reg);
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tcg_temp_free_i32(tmp_ext);
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}
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break;
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default:
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qemu_log_mask(LOG_GUEST_ERROR, "Invalid mts reg 0x%x\n", arg->rs);
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return true;
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}
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dc->cpustate_changed = 1;
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return true;
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#endif
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}
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static bool trans_mfs(DisasContext *dc, arg_mfs *arg)
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{
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TCGv_i32 dest = reg_for_write(dc, arg->rd);
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if (arg->e) {
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switch (arg->rs) {
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case SR_EAR:
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{
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TCGv_i64 t64 = tcg_temp_new_i64();
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tcg_gen_extu_i32_i64(t64, cpu_R[dc->ra]);
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tcg_gen_st_i64(t64, cpu_env, offsetof(CPUMBState, ear));
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tcg_gen_ld_i64(t64, cpu_env, offsetof(CPUMBState, ear));
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tcg_gen_extrh_i64_i32(dest, t64);
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tcg_temp_free_i64(t64);
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}
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return true;
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#ifndef CONFIG_USER_ONLY
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case 0x1003: /* TLBLO */
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/* Handled below. */
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break;
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case SR_ESR:
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tcg_gen_st_i32(cpu_R[dc->ra],
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cpu_env, offsetof(CPUMBState, esr));
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break;
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case SR_FSR:
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tcg_gen_st_i32(cpu_R[dc->ra],
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cpu_env, offsetof(CPUMBState, fsr));
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break;
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case SR_BTR:
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tcg_gen_st_i32(cpu_R[dc->ra],
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cpu_env, offsetof(CPUMBState, btr));
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break;
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case SR_EDR:
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tcg_gen_st_i32(cpu_R[dc->ra],
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cpu_env, offsetof(CPUMBState, edr));
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break;
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case 0x800:
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tcg_gen_st_i32(cpu_R[dc->ra],
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cpu_env, offsetof(CPUMBState, slr));
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break;
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case 0x802:
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tcg_gen_st_i32(cpu_R[dc->ra],
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cpu_env, offsetof(CPUMBState, shr));
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break;
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#endif
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case 0x2006 ... 0x2009:
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/* High bits of PVR6-9 not implemented. */
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tcg_gen_movi_i32(dest, 0);
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return true;
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default:
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cpu_abort(CPU(dc->cpu), "unknown mts reg %x\n", sr);
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break;
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qemu_log_mask(LOG_GUEST_ERROR,
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"Invalid extended mfs reg 0x%x\n", arg->rs);
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return true;
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}
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} else {
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switch (sr) {
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}
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switch (arg->rs) {
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case SR_PC:
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tcg_gen_movi_i32(cpu_R[dc->rd], dc->base.pc_next);
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tcg_gen_movi_i32(dest, dc->base.pc_next);
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break;
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case SR_MSR:
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msr_read(dc, cpu_R[dc->rd]);
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msr_read(dc, dest);
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break;
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case SR_EAR:
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{
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TCGv_i64 t64 = tcg_temp_new_i64();
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tcg_gen_ld_i64(t64, cpu_env, offsetof(CPUMBState, ear));
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if (extended) {
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tcg_gen_extrh_i64_i32(cpu_R[dc->rd], t64);
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} else {
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tcg_gen_extrl_i64_i32(cpu_R[dc->rd], t64);
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}
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tcg_gen_extrl_i64_i32(dest, t64);
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tcg_temp_free_i64(t64);
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}
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break;
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case SR_ESR:
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tcg_gen_ld_i32(cpu_R[dc->rd],
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cpu_env, offsetof(CPUMBState, esr));
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tcg_gen_ld_i32(dest, cpu_env, offsetof(CPUMBState, esr));
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break;
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case SR_FSR:
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tcg_gen_ld_i32(cpu_R[dc->rd],
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cpu_env, offsetof(CPUMBState, fsr));
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tcg_gen_ld_i32(dest, cpu_env, offsetof(CPUMBState, fsr));
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break;
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case SR_BTR:
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tcg_gen_ld_i32(cpu_R[dc->rd],
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cpu_env, offsetof(CPUMBState, btr));
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tcg_gen_ld_i32(dest, cpu_env, offsetof(CPUMBState, btr));
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break;
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case SR_EDR:
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tcg_gen_ld_i32(cpu_R[dc->rd],
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cpu_env, offsetof(CPUMBState, edr));
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tcg_gen_ld_i32(dest, cpu_env, offsetof(CPUMBState, edr));
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break;
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case 0x800:
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tcg_gen_ld_i32(cpu_R[dc->rd],
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cpu_env, offsetof(CPUMBState, slr));
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tcg_gen_ld_i32(dest, cpu_env, offsetof(CPUMBState, slr));
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break;
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case 0x802:
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tcg_gen_ld_i32(cpu_R[dc->rd],
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cpu_env, offsetof(CPUMBState, shr));
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tcg_gen_ld_i32(dest, cpu_env, offsetof(CPUMBState, shr));
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break;
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#ifndef CONFIG_USER_ONLY
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case 0x1000: /* PID */
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case 0x1001: /* ZPR */
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case 0x1002: /* TLBX */
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case 0x1003: /* TLBLO */
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case 0x1004: /* TLBHI */
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case 0x1005: /* TLBSX */
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{
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TCGv_i32 tmp_ext = tcg_const_i32(arg->e);
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TCGv_i32 tmp_reg = tcg_const_i32(arg->rs & 7);
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gen_helper_mmu_read(dest, cpu_env, tmp_ext, tmp_reg);
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tcg_temp_free_i32(tmp_reg);
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tcg_temp_free_i32(tmp_ext);
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}
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break;
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#endif
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case 0x2000 ... 0x200c:
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rn = sr & 0xf;
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tcg_gen_ld_i32(cpu_R[dc->rd],
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cpu_env, offsetof(CPUMBState, pvr.regs[rn]));
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tcg_gen_ld_i32(dest, cpu_env,
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offsetof(CPUMBState, pvr.regs[arg->rs - 0x2000]));
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break;
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default:
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cpu_abort(cs, "unknown mfs reg %x\n", sr);
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qemu_log_mask(LOG_GUEST_ERROR, "Invalid mfs reg 0x%x\n", arg->rs);
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break;
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}
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}
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if (dc->rd == 0) {
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tcg_gen_movi_i32(cpu_R[0], 0);
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}
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return true;
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}
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static void do_rti(DisasContext *dc)
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@ -1593,7 +1596,6 @@ static struct decoder_info {
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};
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void (*dec)(DisasContext *dc);
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} decinfo[] = {
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{DEC_MSR, dec_msr},
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{DEC_STREAM, dec_stream},
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{{0, 0}, dec_null}
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};
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