mirror of https://gitee.com/openkylin/qemu.git
hw/misc/tz-ppc: Model TrustZone peripheral protection controller
Add a model of the TrustZone peripheral protection controller (PPC), which is used to gate transactions to non-TZ-aware peripherals so that secure software can configure them to not be accessible to non-secure software. Signed-off-by: Peter Maydell <peter.maydell@linaro.org> Reviewed-by: Richard Henderson <richard.henderson@linaro.org> Message-id: 20180220180325.29818-15-peter.maydell@linaro.org
This commit is contained in:
Peter Maydell
parent
9a52d9992f
commit
9eb8040c2d
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@ -105,6 +105,8 @@ CONFIG_CMSDK_APB_UART=y
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CONFIG_MPS2_FPGAIO=y
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CONFIG_MPS2_SCC=y
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CONFIG_TZ_PPC=y
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CONFIG_VERSATILE_PCI=y
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CONFIG_VERSATILE_I2C=y
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@ -61,6 +61,8 @@ obj-$(CONFIG_MIPS_ITU) += mips_itu.o
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obj-$(CONFIG_MPS2_FPGAIO) += mps2-fpgaio.o
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obj-$(CONFIG_MPS2_SCC) += mps2-scc.o
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obj-$(CONFIG_TZ_PPC) += tz-ppc.o
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obj-$(CONFIG_PVPANIC) += pvpanic.o
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obj-$(CONFIG_HYPERV_TESTDEV) += hyperv_testdev.o
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obj-$(CONFIG_AUX) += auxbus.o
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@ -83,3 +83,14 @@ mos6522_get_next_irq_time(uint16_t latch, int64_t d, int64_t delta) "latch=%d co
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mos6522_set_sr_int(void) "set sr_int"
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mos6522_write(uint64_t addr, uint64_t val) "reg=0x%"PRIx64 " val=0x%"PRIx64
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mos6522_read(uint64_t addr, unsigned val) "reg=0x%"PRIx64 " val=0x%x"
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# hw/misc/tz-ppc.c
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tz_ppc_reset(void) "TZ PPC: reset"
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tz_ppc_cfg_nonsec(int n, int level) "TZ PPC: cfg_nonsec[%d] = %d"
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tz_ppc_cfg_ap(int n, int level) "TZ PPC: cfg_ap[%d] = %d"
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tz_ppc_cfg_sec_resp(int level) "TZ PPC: cfg_sec_resp = %d"
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tz_ppc_irq_enable(int level) "TZ PPC: int_enable = %d"
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tz_ppc_irq_clear(int level) "TZ PPC: int_clear = %d"
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tz_ppc_update_irq(int level) "TZ PPC: setting irq line to %d"
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tz_ppc_read_blocked(int n, hwaddr offset, bool secure, bool user) "TZ PPC: port %d offset 0x%" HWADDR_PRIx " read (secure %d user %d) blocked"
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tz_ppc_write_blocked(int n, hwaddr offset, bool secure, bool user) "TZ PPC: port %d offset 0x%" HWADDR_PRIx " write (secure %d user %d) blocked"
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@ -0,0 +1,302 @@
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/*
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* ARM TrustZone peripheral protection controller emulation
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*
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* Copyright (c) 2018 Linaro Limited
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* Written by Peter Maydell
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*
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* This program is free software; you can redistribute it and/or modify
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* it under the terms of the GNU General Public License version 2 or
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* (at your option) any later version.
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*/
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#include "qemu/osdep.h"
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#include "qemu/log.h"
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#include "qapi/error.h"
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#include "trace.h"
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#include "hw/sysbus.h"
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#include "hw/registerfields.h"
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#include "hw/misc/tz-ppc.h"
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static void tz_ppc_update_irq(TZPPC *s)
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{
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bool level = s->irq_status && s->irq_enable;
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trace_tz_ppc_update_irq(level);
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qemu_set_irq(s->irq, level);
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}
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static void tz_ppc_cfg_nonsec(void *opaque, int n, int level)
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{
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TZPPC *s = TZ_PPC(opaque);
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assert(n < TZ_NUM_PORTS);
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trace_tz_ppc_cfg_nonsec(n, level);
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s->cfg_nonsec[n] = level;
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}
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static void tz_ppc_cfg_ap(void *opaque, int n, int level)
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{
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TZPPC *s = TZ_PPC(opaque);
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assert(n < TZ_NUM_PORTS);
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trace_tz_ppc_cfg_ap(n, level);
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s->cfg_ap[n] = level;
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}
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static void tz_ppc_cfg_sec_resp(void *opaque, int n, int level)
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{
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TZPPC *s = TZ_PPC(opaque);
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trace_tz_ppc_cfg_sec_resp(level);
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s->cfg_sec_resp = level;
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}
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static void tz_ppc_irq_enable(void *opaque, int n, int level)
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{
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TZPPC *s = TZ_PPC(opaque);
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trace_tz_ppc_irq_enable(level);
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s->irq_enable = level;
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tz_ppc_update_irq(s);
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}
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static void tz_ppc_irq_clear(void *opaque, int n, int level)
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{
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TZPPC *s = TZ_PPC(opaque);
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trace_tz_ppc_irq_clear(level);
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s->irq_clear = level;
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if (level) {
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s->irq_status = false;
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tz_ppc_update_irq(s);
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}
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}
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static bool tz_ppc_check(TZPPC *s, int n, MemTxAttrs attrs)
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{
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/* Check whether to allow an access to port n; return true if
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* the check passes, and false if the transaction must be blocked.
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* If the latter, the caller must check cfg_sec_resp to determine
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* whether to abort or RAZ/WI the transaction.
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* The checks are:
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* + nonsec_mask suppresses any check of the secure attribute
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* + otherwise, block if cfg_nonsec is 1 and transaction is secure,
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* or if cfg_nonsec is 0 and transaction is non-secure
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* + block if transaction is usermode and cfg_ap is 0
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*/
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if ((attrs.secure == s->cfg_nonsec[n] && !(s->nonsec_mask & (1 << n))) ||
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(attrs.user && !s->cfg_ap[n])) {
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/* Block the transaction. */
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if (!s->irq_clear) {
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/* Note that holding irq_clear high suppresses interrupts */
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s->irq_status = true;
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tz_ppc_update_irq(s);
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}
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return false;
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}
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return true;
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}
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static MemTxResult tz_ppc_read(void *opaque, hwaddr addr, uint64_t *pdata,
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unsigned size, MemTxAttrs attrs)
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{
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TZPPCPort *p = opaque;
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TZPPC *s = p->ppc;
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int n = p - s->port;
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AddressSpace *as = &p->downstream_as;
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uint64_t data;
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MemTxResult res;
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if (!tz_ppc_check(s, n, attrs)) {
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trace_tz_ppc_read_blocked(n, addr, attrs.secure, attrs.user);
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if (s->cfg_sec_resp) {
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return MEMTX_ERROR;
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} else {
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*pdata = 0;
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return MEMTX_OK;
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}
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}
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switch (size) {
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case 1:
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data = address_space_ldub(as, addr, attrs, &res);
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break;
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case 2:
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data = address_space_lduw_le(as, addr, attrs, &res);
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break;
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case 4:
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data = address_space_ldl_le(as, addr, attrs, &res);
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break;
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case 8:
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data = address_space_ldq_le(as, addr, attrs, &res);
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break;
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default:
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g_assert_not_reached();
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}
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*pdata = data;
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return res;
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}
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static MemTxResult tz_ppc_write(void *opaque, hwaddr addr, uint64_t val,
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unsigned size, MemTxAttrs attrs)
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{
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TZPPCPort *p = opaque;
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TZPPC *s = p->ppc;
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AddressSpace *as = &p->downstream_as;
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int n = p - s->port;
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MemTxResult res;
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if (!tz_ppc_check(s, n, attrs)) {
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trace_tz_ppc_write_blocked(n, addr, attrs.secure, attrs.user);
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if (s->cfg_sec_resp) {
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return MEMTX_ERROR;
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} else {
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return MEMTX_OK;
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}
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}
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switch (size) {
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case 1:
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address_space_stb(as, addr, val, attrs, &res);
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break;
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case 2:
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address_space_stw_le(as, addr, val, attrs, &res);
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break;
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case 4:
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address_space_stl_le(as, addr, val, attrs, &res);
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break;
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case 8:
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address_space_stq_le(as, addr, val, attrs, &res);
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break;
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default:
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g_assert_not_reached();
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}
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return res;
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}
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static const MemoryRegionOps tz_ppc_ops = {
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.read_with_attrs = tz_ppc_read,
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.write_with_attrs = tz_ppc_write,
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.endianness = DEVICE_LITTLE_ENDIAN,
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};
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static void tz_ppc_reset(DeviceState *dev)
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{
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TZPPC *s = TZ_PPC(dev);
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trace_tz_ppc_reset();
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s->cfg_sec_resp = false;
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memset(s->cfg_nonsec, 0, sizeof(s->cfg_nonsec));
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memset(s->cfg_ap, 0, sizeof(s->cfg_ap));
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}
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static void tz_ppc_init(Object *obj)
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{
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DeviceState *dev = DEVICE(obj);
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TZPPC *s = TZ_PPC(obj);
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qdev_init_gpio_in_named(dev, tz_ppc_cfg_nonsec, "cfg_nonsec", TZ_NUM_PORTS);
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qdev_init_gpio_in_named(dev, tz_ppc_cfg_ap, "cfg_ap", TZ_NUM_PORTS);
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qdev_init_gpio_in_named(dev, tz_ppc_cfg_sec_resp, "cfg_sec_resp", 1);
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qdev_init_gpio_in_named(dev, tz_ppc_irq_enable, "irq_enable", 1);
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qdev_init_gpio_in_named(dev, tz_ppc_irq_clear, "irq_clear", 1);
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qdev_init_gpio_out_named(dev, &s->irq, "irq", 1);
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}
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static void tz_ppc_realize(DeviceState *dev, Error **errp)
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{
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Object *obj = OBJECT(dev);
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SysBusDevice *sbd = SYS_BUS_DEVICE(dev);
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TZPPC *s = TZ_PPC(dev);
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int i;
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/* We can't create the upstream end of the port until realize,
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* as we don't know the size of the MR used as the downstream until then.
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*/
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for (i = 0; i < TZ_NUM_PORTS; i++) {
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TZPPCPort *port = &s->port[i];
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char *name;
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uint64_t size;
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if (!port->downstream) {
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continue;
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}
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name = g_strdup_printf("tz-ppc-port[%d]", i);
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port->ppc = s;
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address_space_init(&port->downstream_as, port->downstream, name);
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size = memory_region_size(port->downstream);
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memory_region_init_io(&port->upstream, obj, &tz_ppc_ops,
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port, name, size);
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sysbus_init_mmio(sbd, &port->upstream);
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g_free(name);
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}
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}
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static const VMStateDescription tz_ppc_vmstate = {
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.name = "tz-ppc",
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.version_id = 1,
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.minimum_version_id = 1,
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.fields = (VMStateField[]) {
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VMSTATE_BOOL_ARRAY(cfg_nonsec, TZPPC, 16),
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VMSTATE_BOOL_ARRAY(cfg_ap, TZPPC, 16),
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VMSTATE_BOOL(cfg_sec_resp, TZPPC),
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VMSTATE_BOOL(irq_enable, TZPPC),
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VMSTATE_BOOL(irq_clear, TZPPC),
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VMSTATE_BOOL(irq_status, TZPPC),
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VMSTATE_END_OF_LIST()
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}
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};
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#define DEFINE_PORT(N) \
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DEFINE_PROP_LINK("port[" #N "]", TZPPC, port[N].downstream, \
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TYPE_MEMORY_REGION, MemoryRegion *)
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static Property tz_ppc_properties[] = {
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DEFINE_PROP_UINT32("NONSEC_MASK", TZPPC, nonsec_mask, 0),
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DEFINE_PORT(0),
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DEFINE_PORT(1),
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DEFINE_PORT(2),
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DEFINE_PORT(3),
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DEFINE_PORT(4),
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DEFINE_PORT(5),
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DEFINE_PORT(6),
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DEFINE_PORT(7),
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DEFINE_PORT(8),
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DEFINE_PORT(9),
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DEFINE_PORT(10),
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DEFINE_PORT(11),
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DEFINE_PORT(12),
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DEFINE_PORT(13),
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DEFINE_PORT(14),
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DEFINE_PORT(15),
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DEFINE_PROP_END_OF_LIST(),
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};
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static void tz_ppc_class_init(ObjectClass *klass, void *data)
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{
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DeviceClass *dc = DEVICE_CLASS(klass);
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dc->realize = tz_ppc_realize;
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dc->vmsd = &tz_ppc_vmstate;
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dc->reset = tz_ppc_reset;
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dc->props = tz_ppc_properties;
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}
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static const TypeInfo tz_ppc_info = {
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.name = TYPE_TZ_PPC,
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.parent = TYPE_SYS_BUS_DEVICE,
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.instance_size = sizeof(TZPPC),
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.instance_init = tz_ppc_init,
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.class_init = tz_ppc_class_init,
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};
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static void tz_ppc_register_types(void)
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{
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type_register_static(&tz_ppc_info);
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}
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type_init(tz_ppc_register_types);
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@ -0,0 +1,101 @@
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/*
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* ARM TrustZone peripheral protection controller emulation
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*
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* Copyright (c) 2018 Linaro Limited
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* Written by Peter Maydell
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*
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* This program is free software; you can redistribute it and/or modify
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* it under the terms of the GNU General Public License version 2 or
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* (at your option) any later version.
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*/
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/* This is a model of the TrustZone peripheral protection controller (PPC).
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* It is documented in the ARM CoreLink SIE-200 System IP for Embedded TRM
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* (DDI 0571G):
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* https://developer.arm.com/products/architecture/m-profile/docs/ddi0571/g
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*
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* The PPC sits in front of peripherals and allows secure software to
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* configure it to either pass through or reject transactions.
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* Rejected transactions may be configured to either be aborted, or to
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* behave as RAZ/WI. An interrupt can be signalled for a rejected transaction.
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*
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* The PPC has no register interface -- it is configured purely by a
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* collection of input signals from other hardware in the system. Typically
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* they are either hardwired or exposed in an ad-hoc register interface by
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* the SoC that uses the PPC.
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*
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* This QEMU model can be used to model either the AHB5 or APB4 TZ PPC,
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* since the only difference between them is that the AHB version has a
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* "default" port which has no security checks applied. In QEMU the default
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* port can be emulated simply by wiring its downstream devices directly
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* into the parent address space, since the PPC does not need to intercept
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* transactions there.
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*
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* In the hardware, selection of which downstream port to use is done by
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* the user's decode logic asserting one of the hsel[] signals. In QEMU,
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* we provide 16 MMIO regions, one per port, and the user maps these into
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* the desired addresses to implement the address decode.
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*
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* QEMU interface:
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* + sysbus MMIO regions 0..15: MemoryRegions defining the upstream end
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* of each of the 16 ports of the PPC
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* + Property "port[0..15]": MemoryRegion defining the downstream device(s)
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* for each of the 16 ports of the PPC
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* + Named GPIO inputs "cfg_nonsec[0..15]": set to 1 if the port should be
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* accessible to NonSecure transactions
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* + Named GPIO inputs "cfg_ap[0..15]": set to 1 if the port should be
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* accessible to non-privileged transactions
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* + Named GPIO input "cfg_sec_resp": set to 1 if a rejected transaction should
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* result in a transaction error, or 0 for the transaction to RAZ/WI
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* + Named GPIO input "irq_enable": set to 1 to enable interrupts
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* + Named GPIO input "irq_clear": set to 1 to clear a pending interrupt
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* + Named GPIO output "irq": set for a transaction-failed interrupt
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* + Property "NONSEC_MASK": if a bit is set in this mask then accesses to
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* the associated port do not have the TZ security check performed. (This
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* corresponds to the hardware allowing this to be set as a Verilog
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* parameter.)
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*/
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#ifndef TZ_PPC_H
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#define TZ_PPC_H
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#include "hw/sysbus.h"
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#define TYPE_TZ_PPC "tz-ppc"
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#define TZ_PPC(obj) OBJECT_CHECK(TZPPC, (obj), TYPE_TZ_PPC)
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#define TZ_NUM_PORTS 16
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typedef struct TZPPC TZPPC;
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typedef struct TZPPCPort {
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TZPPC *ppc;
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MemoryRegion upstream;
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AddressSpace downstream_as;
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MemoryRegion *downstream;
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} TZPPCPort;
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struct TZPPC {
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/*< private >*/
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SysBusDevice parent_obj;
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/*< public >*/
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/* State: these just track the values of our input signals */
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bool cfg_nonsec[TZ_NUM_PORTS];
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bool cfg_ap[TZ_NUM_PORTS];
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bool cfg_sec_resp;
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bool irq_enable;
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bool irq_clear;
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/* State: are we asserting irq ? */
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bool irq_status;
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qemu_irq irq;
|
||||
|
||||
/* Properties */
|
||||
uint32_t nonsec_mask;
|
||||
|
||||
TZPPCPort port[TZ_NUM_PORTS];
|
||||
};
|
||||
|
||||
#endif
|
||||
Loading…
Reference in New Issue