mirror of https://gitee.com/openkylin/qemu.git
sh4 linux-user cpu and hwcap
misc optimizations and cleanup convert r2d to new MMIO accessor style -----BEGIN PGP SIGNATURE----- Version: GnuPG v1 iQIcBAABAgAGBQJVerRbAAoJELqceAYd3YybJlkP/0BUh7cCMDZkVTRMOYVLVW+D a+3Ll86BGt5vavUNmnt2Y3I+VRYVWKObhDU0xo2qBg4WHHX7M62l6Bj6AAF4Lhc0 gu6LPXbf9LyD6300DasV1zwoEyhCS81KFm88SIoe1qGF5ZX3b6MI8/X566YN3ghN 65a1fONz+Bzt2GzKP4i6ABahc3u6GnfuPLa+QWdcsC2cTpUwmAEiU1NSKxjGsTj+ nAzK7AHUsgJodVz+I/KacpD6fAsKi73caPmqdbKH4BTOcQltM806CU5FCcZ7HNVd RH+RnYIT3Uo/RfMkVHkRtZ5NNRg3DP8jb7QEtxY92EseKMPKTO4t/beh9/1ojWrb nWJldPk+a62JBEUMSBIiH5AIyByapo6+H/Vu9tC6hksSpniNXgm3IOZ/dWeQvB3b tU0IuMot9akArngVwHUPWujEREYKGQj+AQlWMzFXNjwDbw7wHIe6xhL4IC5vS9bg 4jlAqeS3Lgkn/YWBH76hYnmeGm0PmylQshNtAZ7dCoYRicdph/pn2vKrWmcDKuHh 7Zw9p5AvK1mCII6/SifbyJ3s/b9cZY5nwmzXWLo2bEUDVqGof6hI7z7AYX8IGNVe NLts5QrFqTChheAmSRRXjUMCoK0AERJOL8B7KIpnJbrCjx2wH+Z1CnXXhB9Xv6Nz 061IiEppJemmMFC0Re3s =t78H -----END PGP SIGNATURE----- Merge remote-tracking branch 'remotes/aurel/tags/pull-sh4-next-20150612' into staging sh4 linux-user cpu and hwcap misc optimizations and cleanup convert r2d to new MMIO accessor style # gpg: Signature made Fri Jun 12 11:28:43 2015 BST using RSA key ID 1DDD8C9B # gpg: Good signature from "Aurelien Jarno <aurelien@aurel32.net>" # gpg: aka "Aurelien Jarno <aurelien@jarno.fr>" # gpg: aka "Aurelien Jarno <aurel32@debian.org>" # gpg: WARNING: This key is not certified with a trusted signature! # gpg: There is no indication that the signature belongs to the owner. # Primary key fingerprint: 7746 2642 A9EF 94FD 0F77 196D BA9C 7806 1DDD 8C9B * remotes/aurel/tags/pull-sh4-next-20150612: target-sh4: remove dead code target-sh4: factorize fmov implementation target-sh4: split out Q and M from of SR and optimize div1 target-sh4: optimize negc using add2 and sub2 target-sh4: optimize subc using sub2 target-sh4: optimize addc using add2 target-sh4: Split out T from SR target-sh4: use bit number for SR constants sh4/r2d: convert to new MMIO accessor style linux-user: Add HWCAP for SH4 linux-user: Default sh4 to sh7785 Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
This commit is contained in:
commit
9faffeb777
12
hw/sh4/r2d.c
12
hw/sh4/r2d.c
|
@ -127,7 +127,7 @@ static void r2d_fpga_irq_set(void *opaque, int n, int level)
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update_irl(fpga);
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}
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static uint32_t r2d_fpga_read(void *opaque, hwaddr addr)
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static uint64_t r2d_fpga_read(void *opaque, hwaddr addr, unsigned int size)
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{
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r2d_fpga_t *s = opaque;
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@ -146,7 +146,7 @@ static uint32_t r2d_fpga_read(void *opaque, hwaddr addr)
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}
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static void
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r2d_fpga_write(void *opaque, hwaddr addr, uint32_t value)
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r2d_fpga_write(void *opaque, hwaddr addr, uint64_t value, unsigned int size)
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{
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r2d_fpga_t *s = opaque;
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@ -170,10 +170,10 @@ r2d_fpga_write(void *opaque, hwaddr addr, uint32_t value)
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}
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static const MemoryRegionOps r2d_fpga_ops = {
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.old_mmio = {
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.read = { r2d_fpga_read, r2d_fpga_read, NULL, },
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.write = { r2d_fpga_write, r2d_fpga_write, NULL, },
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},
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.read = r2d_fpga_read,
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.write = r2d_fpga_write,
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.impl.min_access_size = 2,
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.impl.max_access_size = 2,
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.endianness = DEVICE_NATIVE_ENDIAN,
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};
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@ -1075,6 +1075,35 @@ static inline void elf_core_copy_regs(target_elf_gregset_t *regs,
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#define USE_ELF_CORE_DUMP
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#define ELF_EXEC_PAGESIZE 4096
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enum {
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SH_CPU_HAS_FPU = 0x0001, /* Hardware FPU support */
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SH_CPU_HAS_P2_FLUSH_BUG = 0x0002, /* Need to flush the cache in P2 area */
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SH_CPU_HAS_MMU_PAGE_ASSOC = 0x0004, /* SH3: TLB way selection bit support */
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SH_CPU_HAS_DSP = 0x0008, /* SH-DSP: DSP support */
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SH_CPU_HAS_PERF_COUNTER = 0x0010, /* Hardware performance counters */
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SH_CPU_HAS_PTEA = 0x0020, /* PTEA register */
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SH_CPU_HAS_LLSC = 0x0040, /* movli.l/movco.l */
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SH_CPU_HAS_L2_CACHE = 0x0080, /* Secondary cache / URAM */
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SH_CPU_HAS_OP32 = 0x0100, /* 32-bit instruction support */
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SH_CPU_HAS_PTEAEX = 0x0200, /* PTE ASID Extension support */
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};
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#define ELF_HWCAP get_elf_hwcap()
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static uint32_t get_elf_hwcap(void)
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{
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SuperHCPU *cpu = SUPERH_CPU(thread_cpu);
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uint32_t hwcap = 0;
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hwcap |= SH_CPU_HAS_FPU;
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if (cpu->env.features & SH_FEATURE_SH4A) {
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hwcap |= SH_CPU_HAS_LLSC;
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}
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return hwcap;
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}
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#endif
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#ifdef TARGET_CRIS
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@ -3925,6 +3925,8 @@ int main(int argc, char **argv, char **envp)
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# else
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cpu_model = "750";
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# endif
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#elif defined TARGET_SH4
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cpu_model = TYPE_SH7785_CPU;
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#else
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cpu_model = "any";
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#endif
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@ -61,7 +61,8 @@ static void superh_cpu_reset(CPUState *s)
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env->fpscr = FPSCR_PR; /* value for userspace according to the kernel */
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set_float_rounding_mode(float_round_nearest_even, &env->fp_status); /* ?! */
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#else
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env->sr = SR_MD | SR_RB | SR_BL | SR_I3 | SR_I2 | SR_I1 | SR_I0;
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env->sr = (1u << SR_MD) | (1u << SR_RB) | (1u << SR_BL) |
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(1u << SR_I3) | (1u << SR_I2) | (1u << SR_I1) | (1u << SR_I0);
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env->fpscr = FPSCR_DN | FPSCR_RM_ZERO; /* CPU reset value according to SH4 manual */
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set_float_rounding_mode(float_round_to_zero, &env->fp_status);
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set_flush_to_zero(1, &env->fp_status);
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@ -47,18 +47,18 @@
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#define TARGET_PHYS_ADDR_SPACE_BITS 32
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#define TARGET_VIRT_ADDR_SPACE_BITS 32
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#define SR_MD (1 << 30)
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#define SR_RB (1 << 29)
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#define SR_BL (1 << 28)
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#define SR_FD (1 << 15)
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#define SR_M (1 << 9)
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#define SR_Q (1 << 8)
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#define SR_I3 (1 << 7)
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#define SR_I2 (1 << 6)
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#define SR_I1 (1 << 5)
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#define SR_I0 (1 << 4)
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#define SR_S (1 << 1)
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#define SR_T (1 << 0)
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#define SR_MD 30
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#define SR_RB 29
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#define SR_BL 28
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#define SR_FD 15
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#define SR_M 9
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#define SR_Q 8
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#define SR_I3 7
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#define SR_I2 6
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#define SR_I1 5
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#define SR_I0 4
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#define SR_S 1
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#define SR_T 0
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#define FPSCR_MASK (0x003fffff)
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#define FPSCR_FR (1 << 21)
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@ -138,7 +138,10 @@ typedef struct CPUSH4State {
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uint32_t flags; /* general execution flags */
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uint32_t gregs[24]; /* general registers */
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float32 fregs[32]; /* floating point registers */
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uint32_t sr; /* status register */
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uint32_t sr; /* status register (with T split out) */
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uint32_t sr_m; /* M bit of status register */
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uint32_t sr_q; /* Q bit of status register */
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uint32_t sr_t; /* T bit of status register */
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uint32_t ssr; /* saved status register */
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uint32_t spc; /* saved program counter */
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uint32_t gbr; /* global base register */
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@ -234,7 +237,7 @@ void cpu_load_tlb(CPUSH4State * env);
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#define MMU_USER_IDX 1
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static inline int cpu_mmu_index (CPUSH4State *env)
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{
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return (env->sr & SR_MD) == 0 ? 1 : 0;
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return (env->sr & (1u << SR_MD)) == 0 ? 1 : 0;
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}
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#include "exec/cpu-all.h"
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@ -331,6 +334,21 @@ static inline int cpu_ptel_pr (uint32_t ptel)
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#define TB_FLAG_PENDING_MOVCA (1 << 4)
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static inline target_ulong cpu_read_sr(CPUSH4State *env)
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{
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return env->sr | (env->sr_m << SR_M) |
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(env->sr_q << SR_Q) |
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(env->sr_t << SR_T);
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}
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static inline void cpu_write_sr(CPUSH4State *env, target_ulong sr)
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{
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env->sr_m = (sr >> SR_M) & 1;
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env->sr_q = (sr >> SR_Q) & 1;
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env->sr_t = (sr >> SR_T) & 1;
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env->sr = sr & ~((1u << SR_M) | (1u << SR_Q) | (1u << SR_T));
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}
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static inline void cpu_get_tb_cpu_state(CPUSH4State *env, target_ulong *pc,
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target_ulong *cs_base, int *flags)
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{
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@ -339,8 +357,8 @@ static inline void cpu_get_tb_cpu_state(CPUSH4State *env, target_ulong *pc,
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*flags = (env->flags & (DELAY_SLOT | DELAY_SLOT_CONDITIONAL
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| DELAY_SLOT_TRUE | DELAY_SLOT_CLEARME)) /* Bits 0- 3 */
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| (env->fpscr & (FPSCR_FR | FPSCR_SZ | FPSCR_PR)) /* Bits 19-21 */
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| (env->sr & (SR_MD | SR_RB)) /* Bits 29-30 */
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| (env->sr & SR_FD) /* Bit 15 */
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| (env->sr & ((1u << SR_MD) | (1u << SR_RB))) /* Bits 29-30 */
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| (env->sr & (1u << SR_FD)) /* Bit 15 */
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| (env->movcal_backup ? TB_FLAG_PENDING_MOVCA : 0); /* Bit 4 */
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}
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@ -31,7 +31,7 @@ int superh_cpu_gdb_read_register(CPUState *cs, uint8_t *mem_buf, int n)
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switch (n) {
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case 0 ... 7:
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if ((env->sr & (SR_MD | SR_RB)) == (SR_MD | SR_RB)) {
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if ((env->sr & (1u << SR_MD)) && (env->sr & (1u << SR_RB))) {
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return gdb_get_regl(mem_buf, env->gregs[n + 16]);
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} else {
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return gdb_get_regl(mem_buf, env->gregs[n]);
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@ -51,7 +51,7 @@ int superh_cpu_gdb_read_register(CPUState *cs, uint8_t *mem_buf, int n)
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case 21:
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return gdb_get_regl(mem_buf, env->macl);
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case 22:
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return gdb_get_regl(mem_buf, env->sr);
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return gdb_get_regl(mem_buf, cpu_read_sr(env));
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case 23:
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return gdb_get_regl(mem_buf, env->fpul);
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case 24:
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@ -83,7 +83,7 @@ int superh_cpu_gdb_write_register(CPUState *cs, uint8_t *mem_buf, int n)
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switch (n) {
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case 0 ... 7:
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if ((env->sr & (SR_MD | SR_RB)) == (SR_MD | SR_RB)) {
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if ((env->sr & (1u << SR_MD)) && (env->sr & (1u << SR_RB))) {
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env->gregs[n + 16] = ldl_p(mem_buf);
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} else {
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env->gregs[n] = ldl_p(mem_buf);
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@ -111,7 +111,7 @@ int superh_cpu_gdb_write_register(CPUState *cs, uint8_t *mem_buf, int n)
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env->macl = ldl_p(mem_buf);
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break;
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case 22:
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env->sr = ldl_p(mem_buf);
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cpu_write_sr(env, ldl_p(mem_buf));
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break;
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case 23:
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env->fpul = ldl_p(mem_buf);
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@ -93,7 +93,7 @@ void superh_cpu_do_interrupt(CPUState *cs)
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do_exp = cs->exception_index != -1;
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do_irq = do_irq && (cs->exception_index == -1);
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if (env->sr & SR_BL) {
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if (env->sr & (1u << SR_BL)) {
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if (do_exp && cs->exception_index != 0x1e0) {
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cs->exception_index = 0x000; /* masked exception -> reset */
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}
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@ -162,10 +162,10 @@ void superh_cpu_do_interrupt(CPUState *cs)
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log_cpu_state(cs, 0);
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}
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env->ssr = env->sr;
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env->ssr = cpu_read_sr(env);
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env->spc = env->pc;
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env->sgr = env->gregs[15];
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env->sr |= SR_BL | SR_MD | SR_RB;
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env->sr |= (1u << SR_BL) | (1u << SR_MD) | (1u << SR_RB);
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if (env->flags & (DELAY_SLOT | DELAY_SLOT_CONDITIONAL)) {
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/* Branch instruction should be executed again before delay slot. */
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|
@ -182,7 +182,7 @@ void superh_cpu_do_interrupt(CPUState *cs)
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case 0x000:
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case 0x020:
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case 0x140:
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env->sr &= ~SR_FD;
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env->sr &= ~(1u << SR_FD);
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env->sr |= 0xf << 4; /* IMASK */
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env->pc = 0xa0000000;
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break;
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|
@ -355,23 +355,24 @@ static int get_mmu_address(CPUSH4State * env, target_ulong * physical,
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int use_asid, n;
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tlb_t *matching = NULL;
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use_asid = (env->mmucr & MMUCR_SV) == 0 || (env->sr & SR_MD) == 0;
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use_asid = !(env->mmucr & MMUCR_SV) || !(env->sr & (1u << SR_MD));
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|
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if (rw == 2) {
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n = find_itlb_entry(env, address, use_asid);
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if (n >= 0) {
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matching = &env->itlb[n];
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if (!(env->sr & SR_MD) && !(matching->pr & 2))
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if (!(env->sr & (1u << SR_MD)) && !(matching->pr & 2)) {
|
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n = MMU_ITLB_VIOLATION;
|
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else
|
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} else {
|
||||
*prot = PAGE_EXEC;
|
||||
}
|
||||
} else {
|
||||
n = find_utlb_entry(env, address, use_asid);
|
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if (n >= 0) {
|
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n = copy_utlb_entry_itlb(env, n);
|
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matching = &env->itlb[n];
|
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if (!(env->sr & SR_MD) && !(matching->pr & 2)) {
|
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n = MMU_ITLB_VIOLATION;
|
||||
if (!(env->sr & (1u << SR_MD)) && !(matching->pr & 2)) {
|
||||
n = MMU_ITLB_VIOLATION;
|
||||
} else {
|
||||
*prot = PAGE_READ | PAGE_EXEC;
|
||||
if ((matching->pr & 1) && matching->d) {
|
||||
|
@ -388,7 +389,7 @@ static int get_mmu_address(CPUSH4State * env, target_ulong * physical,
|
|||
n = find_utlb_entry(env, address, use_asid);
|
||||
if (n >= 0) {
|
||||
matching = &env->utlb[n];
|
||||
if (!(env->sr & SR_MD) && !(matching->pr & 2)) {
|
||||
if (!(env->sr & (1u << SR_MD)) && !(matching->pr & 2)) {
|
||||
n = (rw == 1) ? MMU_DTLB_VIOLATION_WRITE :
|
||||
MMU_DTLB_VIOLATION_READ;
|
||||
} else if ((rw == 1) && !(matching->pr & 1)) {
|
||||
|
@ -421,7 +422,7 @@ static int get_physical_address(CPUSH4State * env, target_ulong * physical,
|
|||
/* P1, P2 and P4 areas do not use translation */
|
||||
if ((address >= 0x80000000 && address < 0xc0000000) ||
|
||||
address >= 0xe0000000) {
|
||||
if (!(env->sr & SR_MD)
|
||||
if (!(env->sr & (1u << SR_MD))
|
||||
&& (address < 0xe0000000 || address >= 0xe4000000)) {
|
||||
/* Unauthorized access in user mode (only store queues are available) */
|
||||
fprintf(stderr, "Unauthorized access\n");
|
||||
|
@ -690,7 +691,7 @@ void cpu_sh4_write_mmaped_utlb_addr(CPUSH4State *s, hwaddr addr,
|
|||
uint8_t d = (uint8_t)((mem_value & 0x00000200) >> 9);
|
||||
uint8_t v = (uint8_t)((mem_value & 0x00000100) >> 8);
|
||||
uint8_t asid = (uint8_t)(mem_value & 0x000000ff);
|
||||
int use_asid = (s->mmucr & MMUCR_SV) == 0 || (s->sr & SR_MD) == 0;
|
||||
int use_asid = !(s->mmucr & MMUCR_SV) || !(s->sr & (1u << SR_MD));
|
||||
|
||||
if (associate) {
|
||||
int i;
|
||||
|
@ -821,10 +822,10 @@ void cpu_sh4_write_mmaped_utlb_data(CPUSH4State *s, hwaddr addr,
|
|||
int cpu_sh4_is_cached(CPUSH4State * env, target_ulong addr)
|
||||
{
|
||||
int n;
|
||||
int use_asid = (env->mmucr & MMUCR_SV) == 0 || (env->sr & SR_MD) == 0;
|
||||
int use_asid = !(env->mmucr & MMUCR_SV) || !(env->sr & (1u << SR_MD));
|
||||
|
||||
/* check area */
|
||||
if (env->sr & SR_MD) {
|
||||
if (env->sr & (1u << SR_MD)) {
|
||||
/* For previledged mode, P2 and P4 area is not cachable. */
|
||||
if ((0xA0000000 <= addr && addr < 0xC0000000) || 0xE0000000 <= addr)
|
||||
return 0;
|
||||
|
|
|
@ -11,7 +11,6 @@ DEF_HELPER_3(movcal, void, env, i32, i32)
|
|||
DEF_HELPER_1(discard_movcal_backup, void, env)
|
||||
DEF_HELPER_2(ocbi, void, env, i32)
|
||||
|
||||
DEF_HELPER_3(div1, i32, env, i32, i32)
|
||||
DEF_HELPER_3(macl, void, env, i32, i32)
|
||||
DEF_HELPER_3(macw, void, env, i32, i32)
|
||||
|
||||
|
|
|
@ -156,124 +156,6 @@ void helper_ocbi(CPUSH4State *env, uint32_t address)
|
|||
}
|
||||
}
|
||||
|
||||
#define T (env->sr & SR_T)
|
||||
#define Q (env->sr & SR_Q ? 1 : 0)
|
||||
#define M (env->sr & SR_M ? 1 : 0)
|
||||
#define SETT env->sr |= SR_T
|
||||
#define CLRT env->sr &= ~SR_T
|
||||
#define SETQ env->sr |= SR_Q
|
||||
#define CLRQ env->sr &= ~SR_Q
|
||||
#define SETM env->sr |= SR_M
|
||||
#define CLRM env->sr &= ~SR_M
|
||||
|
||||
uint32_t helper_div1(CPUSH4State *env, uint32_t arg0, uint32_t arg1)
|
||||
{
|
||||
uint32_t tmp0, tmp2;
|
||||
uint8_t old_q, tmp1 = 0xff;
|
||||
|
||||
//printf("div1 arg0=0x%08x arg1=0x%08x M=%d Q=%d T=%d\n", arg0, arg1, M, Q, T);
|
||||
old_q = Q;
|
||||
if ((0x80000000 & arg1) != 0)
|
||||
SETQ;
|
||||
else
|
||||
CLRQ;
|
||||
tmp2 = arg0;
|
||||
arg1 <<= 1;
|
||||
arg1 |= T;
|
||||
switch (old_q) {
|
||||
case 0:
|
||||
switch (M) {
|
||||
case 0:
|
||||
tmp0 = arg1;
|
||||
arg1 -= tmp2;
|
||||
tmp1 = arg1 > tmp0;
|
||||
switch (Q) {
|
||||
case 0:
|
||||
if (tmp1)
|
||||
SETQ;
|
||||
else
|
||||
CLRQ;
|
||||
break;
|
||||
case 1:
|
||||
if (tmp1 == 0)
|
||||
SETQ;
|
||||
else
|
||||
CLRQ;
|
||||
break;
|
||||
}
|
||||
break;
|
||||
case 1:
|
||||
tmp0 = arg1;
|
||||
arg1 += tmp2;
|
||||
tmp1 = arg1 < tmp0;
|
||||
switch (Q) {
|
||||
case 0:
|
||||
if (tmp1 == 0)
|
||||
SETQ;
|
||||
else
|
||||
CLRQ;
|
||||
break;
|
||||
case 1:
|
||||
if (tmp1)
|
||||
SETQ;
|
||||
else
|
||||
CLRQ;
|
||||
break;
|
||||
}
|
||||
break;
|
||||
}
|
||||
break;
|
||||
case 1:
|
||||
switch (M) {
|
||||
case 0:
|
||||
tmp0 = arg1;
|
||||
arg1 += tmp2;
|
||||
tmp1 = arg1 < tmp0;
|
||||
switch (Q) {
|
||||
case 0:
|
||||
if (tmp1)
|
||||
SETQ;
|
||||
else
|
||||
CLRQ;
|
||||
break;
|
||||
case 1:
|
||||
if (tmp1 == 0)
|
||||
SETQ;
|
||||
else
|
||||
CLRQ;
|
||||
break;
|
||||
}
|
||||
break;
|
||||
case 1:
|
||||
tmp0 = arg1;
|
||||
arg1 -= tmp2;
|
||||
tmp1 = arg1 > tmp0;
|
||||
switch (Q) {
|
||||
case 0:
|
||||
if (tmp1 == 0)
|
||||
SETQ;
|
||||
else
|
||||
CLRQ;
|
||||
break;
|
||||
case 1:
|
||||
if (tmp1)
|
||||
SETQ;
|
||||
else
|
||||
CLRQ;
|
||||
break;
|
||||
}
|
||||
break;
|
||||
}
|
||||
break;
|
||||
}
|
||||
if (Q == M)
|
||||
SETT;
|
||||
else
|
||||
CLRT;
|
||||
//printf("Output: arg1=0x%08x M=%d Q=%d T=%d\n", arg1, M, Q, T);
|
||||
return arg1;
|
||||
}
|
||||
|
||||
void helper_macl(CPUSH4State *env, uint32_t arg0, uint32_t arg1)
|
||||
{
|
||||
int64_t res;
|
||||
|
@ -282,7 +164,7 @@ void helper_macl(CPUSH4State *env, uint32_t arg0, uint32_t arg1)
|
|||
res += (int64_t) (int32_t) arg0 *(int64_t) (int32_t) arg1;
|
||||
env->mach = (res >> 32) & 0xffffffff;
|
||||
env->macl = res & 0xffffffff;
|
||||
if (env->sr & SR_S) {
|
||||
if (env->sr & (1u << SR_S)) {
|
||||
if (res < 0)
|
||||
env->mach |= 0xffff0000;
|
||||
else
|
||||
|
@ -298,7 +180,7 @@ void helper_macw(CPUSH4State *env, uint32_t arg0, uint32_t arg1)
|
|||
res += (int64_t) (int16_t) arg0 *(int64_t) (int16_t) arg1;
|
||||
env->mach = (res >> 32) & 0xffffffff;
|
||||
env->macl = res & 0xffffffff;
|
||||
if (env->sr & SR_S) {
|
||||
if (env->sr & (1u << SR_S)) {
|
||||
if (res < -0x80000000) {
|
||||
env->mach = 1;
|
||||
env->macl = 0x80000000;
|
||||
|
@ -309,16 +191,6 @@ void helper_macw(CPUSH4State *env, uint32_t arg0, uint32_t arg1)
|
|||
}
|
||||
}
|
||||
|
||||
static inline void set_t(CPUSH4State *env)
|
||||
{
|
||||
env->sr |= SR_T;
|
||||
}
|
||||
|
||||
static inline void clr_t(CPUSH4State *env)
|
||||
{
|
||||
env->sr &= ~SR_T;
|
||||
}
|
||||
|
||||
void helper_ld_fpscr(CPUSH4State *env, uint32_t val)
|
||||
{
|
||||
env->fpscr = val & FPSCR_MASK;
|
||||
|
@ -403,10 +275,8 @@ void helper_fcmp_eq_FT(CPUSH4State *env, float32 t0, float32 t1)
|
|||
relation = float32_compare(t0, t1, &env->fp_status);
|
||||
if (unlikely(relation == float_relation_unordered)) {
|
||||
update_fpscr(env, GETPC());
|
||||
} else if (relation == float_relation_equal) {
|
||||
set_t(env);
|
||||
} else {
|
||||
clr_t(env);
|
||||
env->sr_t = (relation == float_relation_equal);
|
||||
}
|
||||
}
|
||||
|
||||
|
@ -418,10 +288,8 @@ void helper_fcmp_eq_DT(CPUSH4State *env, float64 t0, float64 t1)
|
|||
relation = float64_compare(t0, t1, &env->fp_status);
|
||||
if (unlikely(relation == float_relation_unordered)) {
|
||||
update_fpscr(env, GETPC());
|
||||
} else if (relation == float_relation_equal) {
|
||||
set_t(env);
|
||||
} else {
|
||||
clr_t(env);
|
||||
env->sr_t = (relation == float_relation_equal);
|
||||
}
|
||||
}
|
||||
|
||||
|
@ -433,10 +301,8 @@ void helper_fcmp_gt_FT(CPUSH4State *env, float32 t0, float32 t1)
|
|||
relation = float32_compare(t0, t1, &env->fp_status);
|
||||
if (unlikely(relation == float_relation_unordered)) {
|
||||
update_fpscr(env, GETPC());
|
||||
} else if (relation == float_relation_greater) {
|
||||
set_t(env);
|
||||
} else {
|
||||
clr_t(env);
|
||||
env->sr_t = (relation == float_relation_greater);
|
||||
}
|
||||
}
|
||||
|
||||
|
@ -448,10 +314,8 @@ void helper_fcmp_gt_DT(CPUSH4State *env, float64 t0, float64 t1)
|
|||
relation = float64_compare(t0, t1, &env->fp_status);
|
||||
if (unlikely(relation == float_relation_unordered)) {
|
||||
update_fpscr(env, GETPC());
|
||||
} else if (relation == float_relation_greater) {
|
||||
set_t(env);
|
||||
} else {
|
||||
clr_t(env);
|
||||
env->sr_t = (relation == float_relation_greater);
|
||||
}
|
||||
}
|
||||
|
||||
|
|
|
@ -18,7 +18,6 @@
|
|||
*/
|
||||
|
||||
#define DEBUG_DISAS
|
||||
//#define SH4_SINGLE_STEP
|
||||
|
||||
#include "cpu.h"
|
||||
#include "disas/disas.h"
|
||||
|
@ -47,7 +46,7 @@ typedef struct DisasContext {
|
|||
#if defined(CONFIG_USER_ONLY)
|
||||
#define IS_USER(ctx) 1
|
||||
#else
|
||||
#define IS_USER(ctx) (!(ctx->flags & SR_MD))
|
||||
#define IS_USER(ctx) (!(ctx->flags & (1u << SR_MD)))
|
||||
#endif
|
||||
|
||||
enum {
|
||||
|
@ -62,7 +61,8 @@ enum {
|
|||
/* global register indexes */
|
||||
static TCGv_ptr cpu_env;
|
||||
static TCGv cpu_gregs[24];
|
||||
static TCGv cpu_pc, cpu_sr, cpu_ssr, cpu_spc, cpu_gbr;
|
||||
static TCGv cpu_sr, cpu_sr_m, cpu_sr_q, cpu_sr_t;
|
||||
static TCGv cpu_pc, cpu_ssr, cpu_spc, cpu_gbr;
|
||||
static TCGv cpu_vbr, cpu_sgr, cpu_dbr, cpu_mach, cpu_macl;
|
||||
static TCGv cpu_pr, cpu_fpscr, cpu_fpul, cpu_ldst;
|
||||
static TCGv cpu_fregs[32];
|
||||
|
@ -110,6 +110,12 @@ void sh4_translate_init(void)
|
|||
offsetof(CPUSH4State, pc), "PC");
|
||||
cpu_sr = tcg_global_mem_new_i32(TCG_AREG0,
|
||||
offsetof(CPUSH4State, sr), "SR");
|
||||
cpu_sr_m = tcg_global_mem_new_i32(TCG_AREG0,
|
||||
offsetof(CPUSH4State, sr_m), "SR_M");
|
||||
cpu_sr_q = tcg_global_mem_new_i32(TCG_AREG0,
|
||||
offsetof(CPUSH4State, sr_q), "SR_Q");
|
||||
cpu_sr_t = tcg_global_mem_new_i32(TCG_AREG0,
|
||||
offsetof(CPUSH4State, sr_t), "SR_T");
|
||||
cpu_ssr = tcg_global_mem_new_i32(TCG_AREG0,
|
||||
offsetof(CPUSH4State, ssr), "SSR");
|
||||
cpu_spc = tcg_global_mem_new_i32(TCG_AREG0,
|
||||
|
@ -156,7 +162,7 @@ void superh_cpu_dump_state(CPUState *cs, FILE *f,
|
|||
CPUSH4State *env = &cpu->env;
|
||||
int i;
|
||||
cpu_fprintf(f, "pc=0x%08x sr=0x%08x pr=0x%08x fpscr=0x%08x\n",
|
||||
env->pc, env->sr, env->pr, env->fpscr);
|
||||
env->pc, cpu_read_sr(env), env->pr, env->fpscr);
|
||||
cpu_fprintf(f, "spc=0x%08x ssr=0x%08x gbr=0x%08x vbr=0x%08x\n",
|
||||
env->spc, env->ssr, env->gbr, env->vbr);
|
||||
cpu_fprintf(f, "sgr=0x%08x dbr=0x%08x delayed_pc=0x%08x fpul=0x%08x\n",
|
||||
|
@ -175,6 +181,30 @@ void superh_cpu_dump_state(CPUState *cs, FILE *f,
|
|||
}
|
||||
}
|
||||
|
||||
static void gen_read_sr(TCGv dst)
|
||||
{
|
||||
TCGv t0 = tcg_temp_new();
|
||||
tcg_gen_shli_i32(t0, cpu_sr_q, SR_Q);
|
||||
tcg_gen_or_i32(dst, dst, t0);
|
||||
tcg_gen_shli_i32(t0, cpu_sr_m, SR_M);
|
||||
tcg_gen_or_i32(dst, dst, t0);
|
||||
tcg_gen_shli_i32(t0, cpu_sr_t, SR_T);
|
||||
tcg_gen_or_i32(dst, cpu_sr, t0);
|
||||
tcg_temp_free_i32(t0);
|
||||
}
|
||||
|
||||
static void gen_write_sr(TCGv src)
|
||||
{
|
||||
tcg_gen_andi_i32(cpu_sr, src,
|
||||
~((1u << SR_Q) | (1u << SR_M) | (1u << SR_T)));
|
||||
tcg_gen_shri_i32(cpu_sr_q, src, SR_Q);
|
||||
tcg_gen_andi_i32(cpu_sr_q, cpu_sr_q, 1);
|
||||
tcg_gen_shri_i32(cpu_sr_m, src, SR_M);
|
||||
tcg_gen_andi_i32(cpu_sr_m, cpu_sr_m, 1);
|
||||
tcg_gen_shri_i32(cpu_sr_t, src, SR_T);
|
||||
tcg_gen_andi_i32(cpu_sr_t, cpu_sr_t, 1);
|
||||
}
|
||||
|
||||
static void gen_goto_tb(DisasContext * ctx, int n, target_ulong dest)
|
||||
{
|
||||
TranslationBlock *tb;
|
||||
|
@ -210,12 +240,9 @@ static void gen_jump(DisasContext * ctx)
|
|||
|
||||
static inline void gen_branch_slot(uint32_t delayed_pc, int t)
|
||||
{
|
||||
TCGv sr;
|
||||
TCGLabel *label = gen_new_label();
|
||||
tcg_gen_movi_i32(cpu_delayed_pc, delayed_pc);
|
||||
sr = tcg_temp_new();
|
||||
tcg_gen_andi_i32(sr, cpu_sr, SR_T);
|
||||
tcg_gen_brcondi_i32(t ? TCG_COND_EQ:TCG_COND_NE, sr, 0, label);
|
||||
tcg_gen_brcondi_i32(t ? TCG_COND_EQ : TCG_COND_NE, cpu_sr_t, 0, label);
|
||||
tcg_gen_ori_i32(cpu_flags, cpu_flags, DELAY_SLOT_TRUE);
|
||||
gen_set_label(label);
|
||||
}
|
||||
|
@ -224,13 +251,8 @@ static inline void gen_branch_slot(uint32_t delayed_pc, int t)
|
|||
static void gen_conditional_jump(DisasContext * ctx,
|
||||
target_ulong ift, target_ulong ifnott)
|
||||
{
|
||||
TCGLabel *l1;
|
||||
TCGv sr;
|
||||
|
||||
l1 = gen_new_label();
|
||||
sr = tcg_temp_new();
|
||||
tcg_gen_andi_i32(sr, cpu_sr, SR_T);
|
||||
tcg_gen_brcondi_i32(TCG_COND_NE, sr, 0, l1);
|
||||
TCGLabel *l1 = gen_new_label();
|
||||
tcg_gen_brcondi_i32(TCG_COND_NE, cpu_sr_t, 0, l1);
|
||||
gen_goto_tb(ctx, 0, ifnott);
|
||||
gen_set_label(l1);
|
||||
gen_goto_tb(ctx, 1, ift);
|
||||
|
@ -252,54 +274,12 @@ static void gen_delayed_conditional_jump(DisasContext * ctx)
|
|||
gen_jump(ctx);
|
||||
}
|
||||
|
||||
static inline void gen_cmp(int cond, TCGv t0, TCGv t1)
|
||||
{
|
||||
TCGv t;
|
||||
|
||||
t = tcg_temp_new();
|
||||
tcg_gen_setcond_i32(cond, t, t1, t0);
|
||||
tcg_gen_andi_i32(cpu_sr, cpu_sr, ~SR_T);
|
||||
tcg_gen_or_i32(cpu_sr, cpu_sr, t);
|
||||
|
||||
tcg_temp_free(t);
|
||||
}
|
||||
|
||||
static inline void gen_cmp_imm(int cond, TCGv t0, int32_t imm)
|
||||
{
|
||||
TCGv t;
|
||||
|
||||
t = tcg_temp_new();
|
||||
tcg_gen_setcondi_i32(cond, t, t0, imm);
|
||||
tcg_gen_andi_i32(cpu_sr, cpu_sr, ~SR_T);
|
||||
tcg_gen_or_i32(cpu_sr, cpu_sr, t);
|
||||
|
||||
tcg_temp_free(t);
|
||||
}
|
||||
|
||||
static inline void gen_store_flags(uint32_t flags)
|
||||
{
|
||||
tcg_gen_andi_i32(cpu_flags, cpu_flags, DELAY_SLOT_TRUE);
|
||||
tcg_gen_ori_i32(cpu_flags, cpu_flags, flags);
|
||||
}
|
||||
|
||||
static inline void gen_copy_bit_i32(TCGv t0, int p0, TCGv t1, int p1)
|
||||
{
|
||||
TCGv tmp = tcg_temp_new();
|
||||
|
||||
p0 &= 0x1f;
|
||||
p1 &= 0x1f;
|
||||
|
||||
tcg_gen_andi_i32(tmp, t1, (1 << p1));
|
||||
tcg_gen_andi_i32(t0, t0, ~(1 << p0));
|
||||
if (p0 < p1)
|
||||
tcg_gen_shri_i32(tmp, tmp, p1 - p0);
|
||||
else if (p0 > p1)
|
||||
tcg_gen_shli_i32(tmp, tmp, p0 - p1);
|
||||
tcg_gen_or_i32(t0, t0, tmp);
|
||||
|
||||
tcg_temp_free(tmp);
|
||||
}
|
||||
|
||||
static inline void gen_load_fpr64(TCGv_i64 t, int reg)
|
||||
{
|
||||
tcg_gen_concat_i32_i64(t, cpu_fregs[reg + 1], cpu_fregs[reg]);
|
||||
|
@ -326,10 +306,12 @@ static inline void gen_store_fpr64 (TCGv_i64 t, int reg)
|
|||
#define B11_8 ((ctx->opcode >> 8) & 0xf)
|
||||
#define B15_12 ((ctx->opcode >> 12) & 0xf)
|
||||
|
||||
#define REG(x) ((x) < 8 && (ctx->flags & (SR_MD | SR_RB)) == (SR_MD | SR_RB) \
|
||||
#define REG(x) ((x) < 8 && (ctx->flags & (1u << SR_MD))\
|
||||
&& (ctx->flags & (1u << SR_RB))\
|
||||
? (cpu_gregs[x + 16]) : (cpu_gregs[x]))
|
||||
|
||||
#define ALTREG(x) ((x) < 8 && (ctx->flags & (SR_MD | SR_RB)) != (SR_MD | SR_RB)\
|
||||
#define ALTREG(x) ((x) < 8 && (!(ctx->flags & (1u << SR_MD))\
|
||||
|| !(ctx->flags & (1u << SR_RB)))\
|
||||
? (cpu_gregs[x + 16]) : (cpu_gregs[x]))
|
||||
|
||||
#define FREG(x) (ctx->flags & FPSCR_FR ? (x) ^ 0x10 : (x))
|
||||
|
@ -359,7 +341,7 @@ static inline void gen_store_fpr64 (TCGv_i64 t, int reg)
|
|||
}
|
||||
|
||||
#define CHECK_FPU_ENABLED \
|
||||
if (ctx->flags & SR_FD) { \
|
||||
if (ctx->flags & (1u << SR_FD)) { \
|
||||
tcg_gen_movi_i32(cpu_pc, ctx->pc); \
|
||||
if (ctx->flags & (DELAY_SLOT | DELAY_SLOT_CONDITIONAL)) { \
|
||||
gen_helper_raise_slot_fpu_disable(cpu_env); \
|
||||
|
@ -409,7 +391,9 @@ static void _decode_opc(DisasContext * ctx)
|
|||
|
||||
switch (ctx->opcode) {
|
||||
case 0x0019: /* div0u */
|
||||
tcg_gen_andi_i32(cpu_sr, cpu_sr, ~(SR_M | SR_Q | SR_T));
|
||||
tcg_gen_movi_i32(cpu_sr_m, 0);
|
||||
tcg_gen_movi_i32(cpu_sr_q, 0);
|
||||
tcg_gen_movi_i32(cpu_sr_t, 0);
|
||||
return;
|
||||
case 0x000b: /* rts */
|
||||
CHECK_NOT_DELAY_SLOT
|
||||
|
@ -422,10 +406,10 @@ static void _decode_opc(DisasContext * ctx)
|
|||
tcg_gen_movi_i32(cpu_macl, 0);
|
||||
return;
|
||||
case 0x0048: /* clrs */
|
||||
tcg_gen_andi_i32(cpu_sr, cpu_sr, ~SR_S);
|
||||
tcg_gen_andi_i32(cpu_sr, cpu_sr, ~(1u << SR_S));
|
||||
return;
|
||||
case 0x0008: /* clrt */
|
||||
tcg_gen_andi_i32(cpu_sr, cpu_sr, ~SR_T);
|
||||
tcg_gen_movi_i32(cpu_sr_t, 0);
|
||||
return;
|
||||
case 0x0038: /* ldtlb */
|
||||
CHECK_PRIVILEGED
|
||||
|
@ -434,16 +418,16 @@ static void _decode_opc(DisasContext * ctx)
|
|||
case 0x002b: /* rte */
|
||||
CHECK_PRIVILEGED
|
||||
CHECK_NOT_DELAY_SLOT
|
||||
tcg_gen_mov_i32(cpu_sr, cpu_ssr);
|
||||
gen_write_sr(cpu_ssr);
|
||||
tcg_gen_mov_i32(cpu_delayed_pc, cpu_spc);
|
||||
ctx->flags |= DELAY_SLOT;
|
||||
ctx->delayed_pc = (uint32_t) - 1;
|
||||
return;
|
||||
case 0x0058: /* sets */
|
||||
tcg_gen_ori_i32(cpu_sr, cpu_sr, SR_S);
|
||||
tcg_gen_ori_i32(cpu_sr, cpu_sr, (1u << SR_S));
|
||||
return;
|
||||
case 0x0018: /* sett */
|
||||
tcg_gen_ori_i32(cpu_sr, cpu_sr, SR_T);
|
||||
tcg_gen_movi_i32(cpu_sr_t, 1);
|
||||
return;
|
||||
case 0xfbfd: /* frchg */
|
||||
tcg_gen_xori_i32(cpu_fpscr, cpu_fpscr, FPSCR_FR);
|
||||
|
@ -659,22 +643,14 @@ static void _decode_opc(DisasContext * ctx)
|
|||
return;
|
||||
case 0x300e: /* addc Rm,Rn */
|
||||
{
|
||||
TCGv t0, t1, t2;
|
||||
t0 = tcg_temp_new();
|
||||
tcg_gen_andi_i32(t0, cpu_sr, SR_T);
|
||||
TCGv t0, t1;
|
||||
t0 = tcg_const_tl(0);
|
||||
t1 = tcg_temp_new();
|
||||
tcg_gen_add_i32(t1, REG(B7_4), REG(B11_8));
|
||||
tcg_gen_add_i32(t0, t0, t1);
|
||||
t2 = tcg_temp_new();
|
||||
tcg_gen_setcond_i32(TCG_COND_GTU, t2, REG(B11_8), t1);
|
||||
tcg_gen_setcond_i32(TCG_COND_GTU, t1, t1, t0);
|
||||
tcg_gen_or_i32(t1, t1, t2);
|
||||
tcg_temp_free(t2);
|
||||
tcg_gen_andi_i32(cpu_sr, cpu_sr, ~SR_T);
|
||||
tcg_gen_or_i32(cpu_sr, cpu_sr, t1);
|
||||
tcg_temp_free(t1);
|
||||
tcg_gen_mov_i32(REG(B11_8), t0);
|
||||
tcg_gen_add2_i32(t1, cpu_sr_t, cpu_sr_t, t0, REG(B7_4), t0);
|
||||
tcg_gen_add2_i32(REG(B11_8), cpu_sr_t,
|
||||
REG(B11_8), t0, t1, cpu_sr_t);
|
||||
tcg_temp_free(t0);
|
||||
tcg_temp_free(t1);
|
||||
}
|
||||
return;
|
||||
case 0x300f: /* addv Rm,Rn */
|
||||
|
@ -686,11 +662,9 @@ static void _decode_opc(DisasContext * ctx)
|
|||
tcg_gen_xor_i32(t1, t0, REG(B11_8));
|
||||
t2 = tcg_temp_new();
|
||||
tcg_gen_xor_i32(t2, REG(B7_4), REG(B11_8));
|
||||
tcg_gen_andc_i32(t1, t1, t2);
|
||||
tcg_gen_andc_i32(cpu_sr_t, t1, t2);
|
||||
tcg_temp_free(t2);
|
||||
tcg_gen_shri_i32(t1, t1, 31);
|
||||
tcg_gen_andi_i32(cpu_sr, cpu_sr, ~SR_T);
|
||||
tcg_gen_or_i32(cpu_sr, cpu_sr, t1);
|
||||
tcg_gen_shri_i32(cpu_sr_t, cpu_sr_t, 31);
|
||||
tcg_temp_free(t1);
|
||||
tcg_gen_mov_i32(REG(B7_4), t0);
|
||||
tcg_temp_free(t0);
|
||||
|
@ -700,54 +674,79 @@ static void _decode_opc(DisasContext * ctx)
|
|||
tcg_gen_and_i32(REG(B11_8), REG(B11_8), REG(B7_4));
|
||||
return;
|
||||
case 0x3000: /* cmp/eq Rm,Rn */
|
||||
gen_cmp(TCG_COND_EQ, REG(B7_4), REG(B11_8));
|
||||
tcg_gen_setcond_i32(TCG_COND_EQ, cpu_sr_t, REG(B11_8), REG(B7_4));
|
||||
return;
|
||||
case 0x3003: /* cmp/ge Rm,Rn */
|
||||
gen_cmp(TCG_COND_GE, REG(B7_4), REG(B11_8));
|
||||
tcg_gen_setcond_i32(TCG_COND_GE, cpu_sr_t, REG(B11_8), REG(B7_4));
|
||||
return;
|
||||
case 0x3007: /* cmp/gt Rm,Rn */
|
||||
gen_cmp(TCG_COND_GT, REG(B7_4), REG(B11_8));
|
||||
tcg_gen_setcond_i32(TCG_COND_GT, cpu_sr_t, REG(B11_8), REG(B7_4));
|
||||
return;
|
||||
case 0x3006: /* cmp/hi Rm,Rn */
|
||||
gen_cmp(TCG_COND_GTU, REG(B7_4), REG(B11_8));
|
||||
tcg_gen_setcond_i32(TCG_COND_GTU, cpu_sr_t, REG(B11_8), REG(B7_4));
|
||||
return;
|
||||
case 0x3002: /* cmp/hs Rm,Rn */
|
||||
gen_cmp(TCG_COND_GEU, REG(B7_4), REG(B11_8));
|
||||
tcg_gen_setcond_i32(TCG_COND_GEU, cpu_sr_t, REG(B11_8), REG(B7_4));
|
||||
return;
|
||||
case 0x200c: /* cmp/str Rm,Rn */
|
||||
{
|
||||
TCGv cmp1 = tcg_temp_new();
|
||||
TCGv cmp2 = tcg_temp_new();
|
||||
tcg_gen_andi_i32(cpu_sr, cpu_sr, ~SR_T);
|
||||
tcg_gen_xor_i32(cmp1, REG(B7_4), REG(B11_8));
|
||||
tcg_gen_andi_i32(cmp2, cmp1, 0xff000000);
|
||||
tcg_gen_setcondi_i32(TCG_COND_EQ, cmp2, cmp2, 0);
|
||||
tcg_gen_or_i32(cpu_sr, cpu_sr, cmp2);
|
||||
tcg_gen_setcondi_i32(TCG_COND_EQ, cpu_sr_t, cmp2, 0);
|
||||
tcg_gen_andi_i32(cmp2, cmp1, 0x00ff0000);
|
||||
tcg_gen_setcondi_i32(TCG_COND_EQ, cmp2, cmp2, 0);
|
||||
tcg_gen_or_i32(cpu_sr, cpu_sr, cmp2);
|
||||
tcg_gen_or_i32(cpu_sr_t, cpu_sr_t, cmp2);
|
||||
tcg_gen_andi_i32(cmp2, cmp1, 0x0000ff00);
|
||||
tcg_gen_setcondi_i32(TCG_COND_EQ, cmp2, cmp2, 0);
|
||||
tcg_gen_or_i32(cpu_sr, cpu_sr, cmp2);
|
||||
tcg_gen_or_i32(cpu_sr_t, cpu_sr_t, cmp2);
|
||||
tcg_gen_andi_i32(cmp2, cmp1, 0x000000ff);
|
||||
tcg_gen_setcondi_i32(TCG_COND_EQ, cmp2, cmp2, 0);
|
||||
tcg_gen_or_i32(cpu_sr, cpu_sr, cmp2);
|
||||
tcg_gen_or_i32(cpu_sr_t, cpu_sr_t, cmp2);
|
||||
tcg_temp_free(cmp2);
|
||||
tcg_temp_free(cmp1);
|
||||
}
|
||||
return;
|
||||
case 0x2007: /* div0s Rm,Rn */
|
||||
{
|
||||
gen_copy_bit_i32(cpu_sr, 8, REG(B11_8), 31); /* SR_Q */
|
||||
gen_copy_bit_i32(cpu_sr, 9, REG(B7_4), 31); /* SR_M */
|
||||
TCGv val = tcg_temp_new();
|
||||
tcg_gen_xor_i32(val, REG(B7_4), REG(B11_8));
|
||||
gen_copy_bit_i32(cpu_sr, 0, val, 31); /* SR_T */
|
||||
tcg_temp_free(val);
|
||||
}
|
||||
tcg_gen_shri_i32(cpu_sr_q, REG(B11_8), 31); /* SR_Q */
|
||||
tcg_gen_shri_i32(cpu_sr_m, REG(B7_4), 31); /* SR_M */
|
||||
tcg_gen_xor_i32(cpu_sr_t, cpu_sr_q, cpu_sr_m); /* SR_T */
|
||||
return;
|
||||
case 0x3004: /* div1 Rm,Rn */
|
||||
gen_helper_div1(REG(B11_8), cpu_env, REG(B7_4), REG(B11_8));
|
||||
{
|
||||
TCGv t0 = tcg_temp_new();
|
||||
TCGv t1 = tcg_temp_new();
|
||||
TCGv t2 = tcg_temp_new();
|
||||
TCGv zero = tcg_const_i32(0);
|
||||
|
||||
/* shift left arg1, saving the bit being pushed out and inserting
|
||||
T on the right */
|
||||
tcg_gen_shri_i32(t0, REG(B11_8), 31);
|
||||
tcg_gen_shli_i32(REG(B11_8), REG(B11_8), 1);
|
||||
tcg_gen_or_i32(REG(B11_8), REG(B11_8), cpu_sr_t);
|
||||
|
||||
/* Add or subtract arg0 from arg1 depending if Q == M. To avoid
|
||||
using 64-bit temps, we compute arg0's high part from q ^ m, so
|
||||
that it is 0x00000000 when adding the value or 0xffffffff when
|
||||
subtracting it. */
|
||||
tcg_gen_xor_i32(t1, cpu_sr_q, cpu_sr_m);
|
||||
tcg_gen_subi_i32(t1, t1, 1);
|
||||
tcg_gen_neg_i32(t2, REG(B7_4));
|
||||
tcg_gen_movcond_i32(TCG_COND_EQ, t2, t1, zero, REG(B7_4), t2);
|
||||
tcg_gen_add2_i32(REG(B11_8), t1, REG(B11_8), zero, t2, t1);
|
||||
|
||||
/* compute T and Q depending on carry */
|
||||
tcg_gen_andi_i32(t1, t1, 1);
|
||||
tcg_gen_xor_i32(t1, t1, t0);
|
||||
tcg_gen_xori_i32(cpu_sr_t, t1, 1);
|
||||
tcg_gen_xor_i32(cpu_sr_q, cpu_sr_m, t1);
|
||||
|
||||
tcg_temp_free(zero);
|
||||
tcg_temp_free(t2);
|
||||
tcg_temp_free(t1);
|
||||
tcg_temp_free(t0);
|
||||
}
|
||||
return;
|
||||
case 0x300d: /* dmuls.l Rm,Rn */
|
||||
tcg_gen_muls2_i32(cpu_macl, cpu_mach, REG(B7_4), REG(B11_8));
|
||||
|
@ -827,19 +826,13 @@ static void _decode_opc(DisasContext * ctx)
|
|||
return;
|
||||
case 0x600a: /* negc Rm,Rn */
|
||||
{
|
||||
TCGv t0, t1;
|
||||
t0 = tcg_temp_new();
|
||||
tcg_gen_neg_i32(t0, REG(B7_4));
|
||||
t1 = tcg_temp_new();
|
||||
tcg_gen_andi_i32(t1, cpu_sr, SR_T);
|
||||
tcg_gen_sub_i32(REG(B11_8), t0, t1);
|
||||
tcg_gen_andi_i32(cpu_sr, cpu_sr, ~SR_T);
|
||||
tcg_gen_setcondi_i32(TCG_COND_GTU, t1, t0, 0);
|
||||
tcg_gen_or_i32(cpu_sr, cpu_sr, t1);
|
||||
tcg_gen_setcond_i32(TCG_COND_GTU, t1, REG(B11_8), t0);
|
||||
tcg_gen_or_i32(cpu_sr, cpu_sr, t1);
|
||||
TCGv t0 = tcg_const_i32(0);
|
||||
tcg_gen_add2_i32(REG(B11_8), cpu_sr_t,
|
||||
REG(B7_4), t0, cpu_sr_t, t0);
|
||||
tcg_gen_sub2_i32(REG(B11_8), cpu_sr_t,
|
||||
t0, t0, REG(B11_8), cpu_sr_t);
|
||||
tcg_gen_andi_i32(cpu_sr_t, cpu_sr_t, 1);
|
||||
tcg_temp_free(t0);
|
||||
tcg_temp_free(t1);
|
||||
}
|
||||
return;
|
||||
case 0x6007: /* not Rm,Rn */
|
||||
|
@ -918,22 +911,15 @@ static void _decode_opc(DisasContext * ctx)
|
|||
return;
|
||||
case 0x300a: /* subc Rm,Rn */
|
||||
{
|
||||
TCGv t0, t1, t2;
|
||||
t0 = tcg_temp_new();
|
||||
tcg_gen_andi_i32(t0, cpu_sr, SR_T);
|
||||
TCGv t0, t1;
|
||||
t0 = tcg_const_tl(0);
|
||||
t1 = tcg_temp_new();
|
||||
tcg_gen_sub_i32(t1, REG(B11_8), REG(B7_4));
|
||||
tcg_gen_sub_i32(t0, t1, t0);
|
||||
t2 = tcg_temp_new();
|
||||
tcg_gen_setcond_i32(TCG_COND_LTU, t2, REG(B11_8), t1);
|
||||
tcg_gen_setcond_i32(TCG_COND_LTU, t1, t1, t0);
|
||||
tcg_gen_or_i32(t1, t1, t2);
|
||||
tcg_temp_free(t2);
|
||||
tcg_gen_andi_i32(cpu_sr, cpu_sr, ~SR_T);
|
||||
tcg_gen_or_i32(cpu_sr, cpu_sr, t1);
|
||||
tcg_temp_free(t1);
|
||||
tcg_gen_mov_i32(REG(B11_8), t0);
|
||||
tcg_gen_add2_i32(t1, cpu_sr_t, cpu_sr_t, t0, REG(B7_4), t0);
|
||||
tcg_gen_sub2_i32(REG(B11_8), cpu_sr_t,
|
||||
REG(B11_8), t0, t1, cpu_sr_t);
|
||||
tcg_gen_andi_i32(cpu_sr_t, cpu_sr_t, 1);
|
||||
tcg_temp_free(t0);
|
||||
tcg_temp_free(t1);
|
||||
}
|
||||
return;
|
||||
case 0x300b: /* subv Rm,Rn */
|
||||
|
@ -947,9 +933,7 @@ static void _decode_opc(DisasContext * ctx)
|
|||
tcg_gen_xor_i32(t2, REG(B11_8), REG(B7_4));
|
||||
tcg_gen_and_i32(t1, t1, t2);
|
||||
tcg_temp_free(t2);
|
||||
tcg_gen_shri_i32(t1, t1, 31);
|
||||
tcg_gen_andi_i32(cpu_sr, cpu_sr, ~SR_T);
|
||||
tcg_gen_or_i32(cpu_sr, cpu_sr, t1);
|
||||
tcg_gen_shri_i32(cpu_sr_t, t1, 31);
|
||||
tcg_temp_free(t1);
|
||||
tcg_gen_mov_i32(REG(B11_8), t0);
|
||||
tcg_temp_free(t0);
|
||||
|
@ -959,7 +943,7 @@ static void _decode_opc(DisasContext * ctx)
|
|||
{
|
||||
TCGv val = tcg_temp_new();
|
||||
tcg_gen_and_i32(val, REG(B7_4), REG(B11_8));
|
||||
gen_cmp_imm(TCG_COND_EQ, val, 0);
|
||||
tcg_gen_setcondi_i32(TCG_COND_EQ, cpu_sr_t, val, 0);
|
||||
tcg_temp_free(val);
|
||||
}
|
||||
return;
|
||||
|
@ -1025,24 +1009,19 @@ static void _decode_opc(DisasContext * ctx)
|
|||
return;
|
||||
case 0xf00b: /* fmov {F,D,X}Rm,@-Rn - FPSCR: Nothing */
|
||||
CHECK_FPU_ENABLED
|
||||
TCGv addr = tcg_temp_new_i32();
|
||||
tcg_gen_subi_i32(addr, REG(B11_8), 4);
|
||||
if (ctx->flags & FPSCR_SZ) {
|
||||
TCGv addr = tcg_temp_new_i32();
|
||||
int fr = XREG(B7_4);
|
||||
tcg_gen_subi_i32(addr, REG(B11_8), 4);
|
||||
tcg_gen_qemu_st_i32(cpu_fregs[fr+1], addr, ctx->memidx, MO_TEUL);
|
||||
tcg_gen_subi_i32(addr, addr, 4);
|
||||
tcg_gen_qemu_st_i32(cpu_fregs[fr], addr, ctx->memidx, MO_TEUL);
|
||||
tcg_gen_mov_i32(REG(B11_8), addr);
|
||||
tcg_temp_free(addr);
|
||||
} else {
|
||||
TCGv addr;
|
||||
addr = tcg_temp_new_i32();
|
||||
tcg_gen_subi_i32(addr, REG(B11_8), 4);
|
||||
tcg_gen_qemu_st_i32(cpu_fregs[FREG(B7_4)], addr,
|
||||
ctx->memidx, MO_TEUL);
|
||||
tcg_gen_mov_i32(REG(B11_8), addr);
|
||||
tcg_temp_free(addr);
|
||||
}
|
||||
tcg_gen_mov_i32(REG(B11_8), addr);
|
||||
tcg_temp_free(addr);
|
||||
return;
|
||||
case 0xf006: /* fmov @(R0,Rm),{F,D,X}Rm - FPSCR: Nothing */
|
||||
CHECK_FPU_ENABLED
|
||||
|
@ -1210,7 +1189,7 @@ static void _decode_opc(DisasContext * ctx)
|
|||
ctx->flags |= DELAY_SLOT_CONDITIONAL;
|
||||
return;
|
||||
case 0x8800: /* cmp/eq #imm,R0 */
|
||||
gen_cmp_imm(TCG_COND_EQ, REG(0), B7_0s);
|
||||
tcg_gen_setcondi_i32(TCG_COND_EQ, cpu_sr_t, REG(0), B7_0s);
|
||||
return;
|
||||
case 0xc400: /* mov.b @(disp,GBR),R0 */
|
||||
{
|
||||
|
@ -1326,7 +1305,7 @@ static void _decode_opc(DisasContext * ctx)
|
|||
{
|
||||
TCGv val = tcg_temp_new();
|
||||
tcg_gen_andi_i32(val, REG(0), B7_0);
|
||||
gen_cmp_imm(TCG_COND_EQ, val, 0);
|
||||
tcg_gen_setcondi_i32(TCG_COND_EQ, cpu_sr_t, val, 0);
|
||||
tcg_temp_free(val);
|
||||
}
|
||||
return;
|
||||
|
@ -1336,7 +1315,7 @@ static void _decode_opc(DisasContext * ctx)
|
|||
tcg_gen_add_i32(val, REG(0), cpu_gbr);
|
||||
tcg_gen_qemu_ld_i32(val, val, ctx->memidx, MO_UB);
|
||||
tcg_gen_andi_i32(val, val, B7_0);
|
||||
gen_cmp_imm(TCG_COND_EQ, val, 0);
|
||||
tcg_gen_setcondi_i32(TCG_COND_EQ, cpu_sr_t, val, 0);
|
||||
tcg_temp_free(val);
|
||||
}
|
||||
return;
|
||||
|
@ -1399,14 +1378,14 @@ static void _decode_opc(DisasContext * ctx)
|
|||
ctx->delayed_pc = (uint32_t) - 1;
|
||||
return;
|
||||
case 0x4015: /* cmp/pl Rn */
|
||||
gen_cmp_imm(TCG_COND_GT, REG(B11_8), 0);
|
||||
tcg_gen_setcondi_i32(TCG_COND_GT, cpu_sr_t, REG(B11_8), 0);
|
||||
return;
|
||||
case 0x4011: /* cmp/pz Rn */
|
||||
gen_cmp_imm(TCG_COND_GE, REG(B11_8), 0);
|
||||
tcg_gen_setcondi_i32(TCG_COND_GE, cpu_sr_t, REG(B11_8), 0);
|
||||
return;
|
||||
case 0x4010: /* dt Rn */
|
||||
tcg_gen_subi_i32(REG(B11_8), REG(B11_8), 1);
|
||||
gen_cmp_imm(TCG_COND_EQ, REG(B11_8), 0);
|
||||
tcg_gen_setcondi_i32(TCG_COND_EQ, cpu_sr_t, REG(B11_8), 0);
|
||||
return;
|
||||
case 0x402b: /* jmp @Rn */
|
||||
CHECK_NOT_DELAY_SLOT
|
||||
|
@ -1423,15 +1402,21 @@ static void _decode_opc(DisasContext * ctx)
|
|||
return;
|
||||
case 0x400e: /* ldc Rm,SR */
|
||||
CHECK_PRIVILEGED
|
||||
tcg_gen_andi_i32(cpu_sr, REG(B11_8), 0x700083f3);
|
||||
ctx->bstate = BS_STOP;
|
||||
{
|
||||
TCGv val = tcg_temp_new();
|
||||
tcg_gen_andi_i32(val, REG(B11_8), 0x700083f3);
|
||||
gen_write_sr(val);
|
||||
tcg_temp_free(val);
|
||||
ctx->bstate = BS_STOP;
|
||||
}
|
||||
return;
|
||||
case 0x4007: /* ldc.l @Rm+,SR */
|
||||
CHECK_PRIVILEGED
|
||||
{
|
||||
TCGv val = tcg_temp_new();
|
||||
tcg_gen_qemu_ld_i32(val, REG(B11_8), ctx->memidx, MO_TESL);
|
||||
tcg_gen_andi_i32(cpu_sr, val, 0x700083f3);
|
||||
tcg_gen_andi_i32(val, val, 0x700083f3);
|
||||
gen_write_sr(val);
|
||||
tcg_temp_free(val);
|
||||
tcg_gen_addi_i32(REG(B11_8), REG(B11_8), 4);
|
||||
ctx->bstate = BS_STOP;
|
||||
|
@ -1439,15 +1424,18 @@ static void _decode_opc(DisasContext * ctx)
|
|||
return;
|
||||
case 0x0002: /* stc SR,Rn */
|
||||
CHECK_PRIVILEGED
|
||||
tcg_gen_mov_i32(REG(B11_8), cpu_sr);
|
||||
gen_read_sr(REG(B11_8));
|
||||
return;
|
||||
case 0x4003: /* stc SR,@-Rn */
|
||||
CHECK_PRIVILEGED
|
||||
{
|
||||
TCGv addr = tcg_temp_new();
|
||||
TCGv val = tcg_temp_new();
|
||||
tcg_gen_subi_i32(addr, REG(B11_8), 4);
|
||||
tcg_gen_qemu_st_i32(cpu_sr, addr, ctx->memidx, MO_TEUL);
|
||||
gen_read_sr(val);
|
||||
tcg_gen_qemu_st_i32(val, addr, ctx->memidx, MO_TEUL);
|
||||
tcg_gen_mov_i32(REG(B11_8), addr);
|
||||
tcg_temp_free(val);
|
||||
tcg_temp_free(addr);
|
||||
}
|
||||
return;
|
||||
|
@ -1545,7 +1533,7 @@ static void _decode_opc(DisasContext * ctx)
|
|||
tcg_gen_addi_i32(REG(B11_8), REG(B11_8), 4);
|
||||
return;
|
||||
case 0x0029: /* movt Rn */
|
||||
tcg_gen_andi_i32(REG(B11_8), cpu_sr, SR_T);
|
||||
tcg_gen_mov_i32(REG(B11_8), cpu_sr_t);
|
||||
return;
|
||||
case 0x0073:
|
||||
/* MOVCO.L
|
||||
|
@ -1555,8 +1543,7 @@ static void _decode_opc(DisasContext * ctx)
|
|||
*/
|
||||
if (ctx->features & SH_FEATURE_SH4A) {
|
||||
TCGLabel *label = gen_new_label();
|
||||
tcg_gen_andi_i32(cpu_sr, cpu_sr, ~SR_T);
|
||||
tcg_gen_or_i32(cpu_sr, cpu_sr, cpu_ldst);
|
||||
tcg_gen_mov_i32(cpu_sr_t, cpu_ldst);
|
||||
tcg_gen_brcondi_i32(TCG_COND_EQ, cpu_ldst, 0, label);
|
||||
tcg_gen_qemu_st_i32(REG(0), REG(B11_8), ctx->memidx, MO_TEUL);
|
||||
gen_set_label(label);
|
||||
|
@ -1609,42 +1596,42 @@ static void _decode_opc(DisasContext * ctx)
|
|||
case 0x4024: /* rotcl Rn */
|
||||
{
|
||||
TCGv tmp = tcg_temp_new();
|
||||
tcg_gen_mov_i32(tmp, cpu_sr);
|
||||
gen_copy_bit_i32(cpu_sr, 0, REG(B11_8), 31);
|
||||
tcg_gen_mov_i32(tmp, cpu_sr_t);
|
||||
tcg_gen_shri_i32(cpu_sr_t, REG(B11_8), 31);
|
||||
tcg_gen_shli_i32(REG(B11_8), REG(B11_8), 1);
|
||||
gen_copy_bit_i32(REG(B11_8), 0, tmp, 0);
|
||||
tcg_gen_or_i32(REG(B11_8), REG(B11_8), tmp);
|
||||
tcg_temp_free(tmp);
|
||||
}
|
||||
return;
|
||||
case 0x4025: /* rotcr Rn */
|
||||
{
|
||||
TCGv tmp = tcg_temp_new();
|
||||
tcg_gen_mov_i32(tmp, cpu_sr);
|
||||
gen_copy_bit_i32(cpu_sr, 0, REG(B11_8), 0);
|
||||
tcg_gen_shli_i32(tmp, cpu_sr_t, 31);
|
||||
tcg_gen_andi_i32(cpu_sr_t, REG(B11_8), 1);
|
||||
tcg_gen_shri_i32(REG(B11_8), REG(B11_8), 1);
|
||||
gen_copy_bit_i32(REG(B11_8), 31, tmp, 0);
|
||||
tcg_gen_or_i32(REG(B11_8), REG(B11_8), tmp);
|
||||
tcg_temp_free(tmp);
|
||||
}
|
||||
return;
|
||||
case 0x4004: /* rotl Rn */
|
||||
tcg_gen_rotli_i32(REG(B11_8), REG(B11_8), 1);
|
||||
gen_copy_bit_i32(cpu_sr, 0, REG(B11_8), 0);
|
||||
tcg_gen_andi_i32(cpu_sr_t, REG(B11_8), 0);
|
||||
return;
|
||||
case 0x4005: /* rotr Rn */
|
||||
gen_copy_bit_i32(cpu_sr, 0, REG(B11_8), 0);
|
||||
tcg_gen_andi_i32(cpu_sr_t, REG(B11_8), 0);
|
||||
tcg_gen_rotri_i32(REG(B11_8), REG(B11_8), 1);
|
||||
return;
|
||||
case 0x4000: /* shll Rn */
|
||||
case 0x4020: /* shal Rn */
|
||||
gen_copy_bit_i32(cpu_sr, 0, REG(B11_8), 31);
|
||||
tcg_gen_shri_i32(cpu_sr_t, REG(B11_8), 31);
|
||||
tcg_gen_shli_i32(REG(B11_8), REG(B11_8), 1);
|
||||
return;
|
||||
case 0x4021: /* shar Rn */
|
||||
gen_copy_bit_i32(cpu_sr, 0, REG(B11_8), 0);
|
||||
tcg_gen_andi_i32(cpu_sr_t, REG(B11_8), 1);
|
||||
tcg_gen_sari_i32(REG(B11_8), REG(B11_8), 1);
|
||||
return;
|
||||
case 0x4001: /* shlr Rn */
|
||||
gen_copy_bit_i32(cpu_sr, 0, REG(B11_8), 0);
|
||||
tcg_gen_andi_i32(cpu_sr_t, REG(B11_8), 1);
|
||||
tcg_gen_shri_i32(REG(B11_8), REG(B11_8), 1);
|
||||
return;
|
||||
case 0x4008: /* shll2 Rn */
|
||||
|
@ -1672,7 +1659,7 @@ static void _decode_opc(DisasContext * ctx)
|
|||
tcg_gen_mov_i32(addr, REG(B11_8));
|
||||
val = tcg_temp_local_new();
|
||||
tcg_gen_qemu_ld_i32(val, addr, ctx->memidx, MO_UB);
|
||||
gen_cmp_imm(TCG_COND_EQ, val, 0);
|
||||
tcg_gen_setcondi_i32(TCG_COND_EQ, cpu_sr_t, val, 0);
|
||||
tcg_gen_ori_i32(val, val, 0x80);
|
||||
tcg_gen_qemu_st_i32(val, addr, ctx->memidx, MO_UB);
|
||||
tcg_temp_free(val);
|
||||
|
@ -1874,7 +1861,7 @@ gen_intermediate_code_internal(SuperHCPU *cpu, TranslationBlock *tb,
|
|||
ctx.pc = pc_start;
|
||||
ctx.flags = (uint32_t)tb->flags;
|
||||
ctx.bstate = BS_NONE;
|
||||
ctx.memidx = (ctx.flags & SR_MD) == 0 ? 1 : 0;
|
||||
ctx.memidx = (ctx.flags & (1u << SR_MD)) == 0 ? 1 : 0;
|
||||
/* We don't know if the delayed pc came from a dynamic or static branch,
|
||||
so assume it is a dynamic branch. */
|
||||
ctx.delayed_pc = -1; /* use delayed pc from env pointer */
|
||||
|
|
Loading…
Reference in New Issue