mirror of https://gitee.com/openkylin/qemu.git
Start implementing pSeries logical partition machine
This patch adds a "pseries" machine to qemu. This aims to emulate a logical partition on an IBM pSeries machine, compliant to the "PowerPC Architecture Platform Requirements" (PAPR) document. This initial version is quite limited, it implements a basic machine and PAPR hypercall emulation. So far only one hypercall is present - H_PUT_TERM_CHAR - so that a (write-only) console is available. Multiple CPUs are permitted, with SMP entry handled kexec() style. The machine so far more resembles an old POWER4 style "full system partition" rather than a modern LPAR, in that the guest manages the page tables directly, rather than via hypercalls. The machine requires qemu to be configured with --enable-fdt. The machine can (so far) only be booted with -kernel - i.e. no partition firmware is provided. Signed-off-by: David Gibson <dwg@au1.ibm.com> Signed-off-by: Alexander Graf <agraf@suse.de>
This commit is contained in:
David Gibson
Alexander Graf
parent
9d52e9079d
commit
9fdf0c2995
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@ -231,6 +231,10 @@ obj-ppc-y += ppc_prep.o
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obj-ppc-y += ppc_oldworld.o
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# NewWorld PowerMac
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obj-ppc-y += ppc_newworld.o
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# IBM pSeries (sPAPR)i
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ifeq ($(CONFIG_FDT)$(TARGET_PPC64),yy)
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obj-ppc-y += spapr.o spapr_hcall.o
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endif
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# PowerPC 4xx boards
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obj-ppc-y += ppc4xx_devs.o ppc4xx_pci.o ppc405_uc.o ppc405_boards.o
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obj-ppc-y += ppc440.o ppc440_bamboo.o
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@ -0,0 +1,313 @@
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/*
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* QEMU PowerPC pSeries Logical Partition (aka sPAPR) hardware System Emulator
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*
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* Copyright (c) 2004-2007 Fabrice Bellard
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* Copyright (c) 2007 Jocelyn Mayer
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* Copyright (c) 2010 David Gibson, IBM Corporation.
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*
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* Permission is hereby granted, free of charge, to any person obtaining a copy
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* of this software and associated documentation files (the "Software"), to deal
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* in the Software without restriction, including without limitation the rights
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* to use, copy, modify, merge, publish, distribute, sublicense, and/or sell
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* copies of the Software, and to permit persons to whom the Software is
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* furnished to do so, subject to the following conditions:
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*
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* The above copyright notice and this permission notice shall be included in
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* all copies or substantial portions of the Software.
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*
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* THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
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* IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
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* FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
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* THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
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* LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM,
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* OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN
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* THE SOFTWARE.
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*
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*/
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#include "sysemu.h"
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#include "qemu-char.h"
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#include "hw.h"
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#include "elf.h"
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#include "hw/boards.h"
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#include "hw/ppc.h"
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#include "hw/loader.h"
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#include "hw/spapr.h"
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#include <libfdt.h>
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#define KERNEL_LOAD_ADDR 0x00000000
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#define INITRD_LOAD_ADDR 0x02800000
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#define FDT_MAX_SIZE 0x10000
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#define TIMEBASE_FREQ 512000000ULL
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#define MAX_CPUS 32
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sPAPREnvironment *spapr;
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static void *spapr_create_fdt(int *fdt_size, ram_addr_t ramsize,
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const char *cpu_model, CPUState *envs[],
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sPAPREnvironment *spapr,
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target_phys_addr_t initrd_base,
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target_phys_addr_t initrd_size,
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const char *kernel_cmdline)
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{
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void *fdt;
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uint64_t mem_reg_property[] = { 0, cpu_to_be64(ramsize) };
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uint32_t start_prop = cpu_to_be32(initrd_base);
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uint32_t end_prop = cpu_to_be32(initrd_base + initrd_size);
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int i;
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char *modelname;
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#define _FDT(exp) \
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do { \
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int ret = (exp); \
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if (ret < 0) { \
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fprintf(stderr, "qemu: error creating device tree: %s: %s\n", \
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#exp, fdt_strerror(ret)); \
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exit(1); \
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} \
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} while (0)
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fdt = qemu_mallocz(FDT_MAX_SIZE);
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_FDT((fdt_create(fdt, FDT_MAX_SIZE)));
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_FDT((fdt_finish_reservemap(fdt)));
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/* Root node */
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_FDT((fdt_begin_node(fdt, "")));
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_FDT((fdt_property_string(fdt, "device_type", "chrp")));
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_FDT((fdt_property_string(fdt, "model", "qemu,emulated-pSeries-LPAR")));
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_FDT((fdt_property_cell(fdt, "#address-cells", 0x2)));
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_FDT((fdt_property_cell(fdt, "#size-cells", 0x2)));
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/* /chosen */
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_FDT((fdt_begin_node(fdt, "chosen")));
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_FDT((fdt_property_string(fdt, "bootargs", kernel_cmdline)));
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_FDT((fdt_property(fdt, "linux,initrd-start",
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&start_prop, sizeof(start_prop))));
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_FDT((fdt_property(fdt, "linux,initrd-end",
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&end_prop, sizeof(end_prop))));
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_FDT((fdt_end_node(fdt)));
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/* memory node */
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_FDT((fdt_begin_node(fdt, "memory@0")));
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_FDT((fdt_property_string(fdt, "device_type", "memory")));
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_FDT((fdt_property(fdt, "reg",
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mem_reg_property, sizeof(mem_reg_property))));
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_FDT((fdt_end_node(fdt)));
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/* cpus */
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_FDT((fdt_begin_node(fdt, "cpus")));
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_FDT((fdt_property_cell(fdt, "#address-cells", 0x1)));
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_FDT((fdt_property_cell(fdt, "#size-cells", 0x0)));
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modelname = qemu_strdup(cpu_model);
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for (i = 0; i < strlen(modelname); i++) {
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modelname[i] = toupper(modelname[i]);
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}
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for (i = 0; i < smp_cpus; i++) {
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CPUState *env = envs[i];
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char *nodename;
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uint32_t segs[] = {cpu_to_be32(28), cpu_to_be32(40),
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0xffffffff, 0xffffffff};
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if (asprintf(&nodename, "%s@%x", modelname, i) < 0) {
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fprintf(stderr, "Allocation failure\n");
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exit(1);
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}
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_FDT((fdt_begin_node(fdt, nodename)));
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free(nodename);
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_FDT((fdt_property_cell(fdt, "reg", i)));
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_FDT((fdt_property_string(fdt, "device_type", "cpu")));
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_FDT((fdt_property_cell(fdt, "cpu-version", env->spr[SPR_PVR])));
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_FDT((fdt_property_cell(fdt, "dcache-block-size",
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env->dcache_line_size)));
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_FDT((fdt_property_cell(fdt, "icache-block-size",
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env->icache_line_size)));
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_FDT((fdt_property_cell(fdt, "timebase-frequency", TIMEBASE_FREQ)));
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/* Hardcode CPU frequency for now. It's kind of arbitrary on
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* full emu, for kvm we should copy it from the host */
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_FDT((fdt_property_cell(fdt, "clock-frequency", 1000000000)));
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_FDT((fdt_property_cell(fdt, "ibm,slb-size", env->slb_nr)));
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_FDT((fdt_property_string(fdt, "status", "okay")));
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_FDT((fdt_property(fdt, "64-bit", NULL, 0)));
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if (envs[i]->mmu_model & POWERPC_MMU_1TSEG) {
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_FDT((fdt_property(fdt, "ibm,processor-segment-sizes",
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segs, sizeof(segs))));
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}
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_FDT((fdt_end_node(fdt)));
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}
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qemu_free(modelname);
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_FDT((fdt_end_node(fdt)));
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_FDT((fdt_end_node(fdt))); /* close root node */
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_FDT((fdt_finish(fdt)));
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*fdt_size = fdt_totalsize(fdt);
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return fdt;
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}
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static uint64_t translate_kernel_address(void *opaque, uint64_t addr)
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{
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return (addr & 0x0fffffff) + KERNEL_LOAD_ADDR;
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}
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static void emulate_spapr_hypercall(CPUState *env)
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{
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env->gpr[3] = spapr_hypercall(env, env->gpr[3], &env->gpr[4]);
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}
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/* FIXME: hack until we implement the proper VIO console */
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static target_ulong h_put_term_char(CPUState *env, sPAPREnvironment *spapr,
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target_ulong opcode, target_ulong *args)
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{
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uint8_t buf[16];
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stq_p(buf, args[2]);
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stq_p(buf + 8, args[3]);
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qemu_chr_write(serial_hds[0], buf, args[1]);
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return 0;
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}
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/* pSeries LPAR / sPAPR hardware init */
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static void ppc_spapr_init(ram_addr_t ram_size,
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const char *boot_device,
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const char *kernel_filename,
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const char *kernel_cmdline,
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const char *initrd_filename,
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const char *cpu_model)
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{
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CPUState *envs[MAX_CPUS];
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void *fdt;
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int i;
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ram_addr_t ram_offset;
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target_phys_addr_t fdt_addr;
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uint32_t kernel_base, initrd_base;
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long kernel_size, initrd_size;
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int fdt_size;
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spapr = qemu_malloc(sizeof(*spapr));
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cpu_ppc_hypercall = emulate_spapr_hypercall;
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/* We place the device tree just below either the top of RAM, or
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* 2GB, so that it can be processed with 32-bit code if
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* necessary */
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fdt_addr = MIN(ram_size, 0x80000000) - FDT_MAX_SIZE;
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/* init CPUs */
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if (cpu_model == NULL) {
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cpu_model = "POWER7";
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}
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for (i = 0; i < smp_cpus; i++) {
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CPUState *env = cpu_init(cpu_model);
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if (!env) {
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fprintf(stderr, "Unable to find PowerPC CPU definition\n");
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exit(1);
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}
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/* Set time-base frequency to 512 MHz */
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cpu_ppc_tb_init(env, TIMEBASE_FREQ);
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qemu_register_reset((QEMUResetHandler *)&cpu_reset, env);
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env->hreset_vector = 0x60;
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env->hreset_excp_prefix = 0;
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env->gpr[3] = i;
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envs[i] = env;
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}
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/* allocate RAM */
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ram_offset = qemu_ram_alloc(NULL, "ppc_spapr.ram", ram_size);
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cpu_register_physical_memory(0, ram_size, ram_offset);
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spapr_register_hypercall(H_PUT_TERM_CHAR, h_put_term_char);
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if (kernel_filename) {
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uint64_t lowaddr = 0;
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kernel_base = KERNEL_LOAD_ADDR;
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kernel_size = load_elf(kernel_filename, translate_kernel_address, NULL,
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NULL, &lowaddr, NULL, 1, ELF_MACHINE, 0);
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if (kernel_size < 0) {
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kernel_size = load_image_targphys(kernel_filename, kernel_base,
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ram_size - kernel_base);
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}
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if (kernel_size < 0) {
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fprintf(stderr, "qemu: could not load kernel '%s'\n",
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kernel_filename);
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exit(1);
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}
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/* load initrd */
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if (initrd_filename) {
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initrd_base = INITRD_LOAD_ADDR;
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initrd_size = load_image_targphys(initrd_filename, initrd_base,
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ram_size - initrd_base);
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if (initrd_size < 0) {
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fprintf(stderr, "qemu: could not load initial ram disk '%s'\n",
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initrd_filename);
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exit(1);
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}
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} else {
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initrd_base = 0;
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initrd_size = 0;
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}
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} else {
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fprintf(stderr, "pSeries machine needs -kernel for now");
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exit(1);
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}
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/* Prepare the device tree */
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fdt = spapr_create_fdt(&fdt_size, ram_size, cpu_model, envs, spapr,
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initrd_base, initrd_size, kernel_cmdline);
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assert(fdt != NULL);
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cpu_physical_memory_write(fdt_addr, fdt, fdt_size);
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qemu_free(fdt);
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envs[0]->gpr[3] = fdt_addr;
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envs[0]->gpr[5] = 0;
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envs[0]->hreset_vector = kernel_base;
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}
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static QEMUMachine spapr_machine = {
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.name = "pseries",
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.desc = "pSeries Logical Partition (PAPR compliant)",
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.init = ppc_spapr_init,
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.max_cpus = MAX_CPUS,
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.no_vga = 1,
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.no_parallel = 1,
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};
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static void spapr_machine_init(void)
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{
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qemu_register_machine(&spapr_machine);
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}
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machine_init(spapr_machine_init);
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@ -0,0 +1,257 @@
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#if !defined(__HW_SPAPR_H__)
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#define __HW_SPAPR_H__
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typedef struct sPAPREnvironment {
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} sPAPREnvironment;
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#define H_SUCCESS 0
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#define H_BUSY 1 /* Hardware busy -- retry later */
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#define H_CLOSED 2 /* Resource closed */
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#define H_NOT_AVAILABLE 3
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#define H_CONSTRAINED 4 /* Resource request constrained to max allowed */
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#define H_PARTIAL 5
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#define H_IN_PROGRESS 14 /* Kind of like busy */
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#define H_PAGE_REGISTERED 15
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#define H_PARTIAL_STORE 16
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#define H_PENDING 17 /* returned from H_POLL_PENDING */
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#define H_CONTINUE 18 /* Returned from H_Join on success */
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#define H_LONG_BUSY_START_RANGE 9900 /* Start of long busy range */
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#define H_LONG_BUSY_ORDER_1_MSEC 9900 /* Long busy, hint that 1msec \
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is a good time to retry */
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#define H_LONG_BUSY_ORDER_10_MSEC 9901 /* Long busy, hint that 10msec \
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is a good time to retry */
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#define H_LONG_BUSY_ORDER_100_MSEC 9902 /* Long busy, hint that 100msec \
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is a good time to retry */
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#define H_LONG_BUSY_ORDER_1_SEC 9903 /* Long busy, hint that 1sec \
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is a good time to retry */
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#define H_LONG_BUSY_ORDER_10_SEC 9904 /* Long busy, hint that 10sec \
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is a good time to retry */
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#define H_LONG_BUSY_ORDER_100_SEC 9905 /* Long busy, hint that 100sec \
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is a good time to retry */
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#define H_LONG_BUSY_END_RANGE 9905 /* End of long busy range */
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#define H_HARDWARE -1 /* Hardware error */
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#define H_FUNCTION -2 /* Function not supported */
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#define H_PRIVILEGE -3 /* Caller not privileged */
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#define H_PARAMETER -4 /* Parameter invalid, out-of-range or conflicting */
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#define H_BAD_MODE -5 /* Illegal msr value */
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#define H_PTEG_FULL -6 /* PTEG is full */
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#define H_NOT_FOUND -7 /* PTE was not found" */
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#define H_RESERVED_DABR -8 /* DABR address is reserved by the hypervisor on this processor" */
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#define H_NO_MEM -9
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#define H_AUTHORITY -10
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#define H_PERMISSION -11
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#define H_DROPPED -12
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#define H_SOURCE_PARM -13
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#define H_DEST_PARM -14
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#define H_REMOTE_PARM -15
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#define H_RESOURCE -16
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#define H_ADAPTER_PARM -17
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#define H_RH_PARM -18
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#define H_RCQ_PARM -19
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#define H_SCQ_PARM -20
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#define H_EQ_PARM -21
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#define H_RT_PARM -22
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#define H_ST_PARM -23
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#define H_SIGT_PARM -24
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#define H_TOKEN_PARM -25
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#define H_MLENGTH_PARM -27
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#define H_MEM_PARM -28
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#define H_MEM_ACCESS_PARM -29
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#define H_ATTR_PARM -30
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#define H_PORT_PARM -31
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#define H_MCG_PARM -32
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#define H_VL_PARM -33
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#define H_TSIZE_PARM -34
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#define H_TRACE_PARM -35
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#define H_MASK_PARM -37
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#define H_MCG_FULL -38
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#define H_ALIAS_EXIST -39
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#define H_P_COUNTER -40
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#define H_TABLE_FULL -41
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#define H_ALT_TABLE -42
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#define H_MR_CONDITION -43
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#define H_NOT_ENOUGH_RESOURCES -44
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#define H_R_STATE -45
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#define H_RESCINDEND -46
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#define H_MULTI_THREADS_ACTIVE -9005
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/* Long Busy is a condition that can be returned by the firmware
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* when a call cannot be completed now, but the identical call
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* should be retried later. This prevents calls blocking in the
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* firmware for long periods of time. Annoyingly the firmware can return
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* a range of return codes, hinting at how long we should wait before
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* retrying. If you don't care for the hint, the macro below is a good
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* way to check for the long_busy return codes
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*/
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#define H_IS_LONG_BUSY(x) ((x >= H_LONG_BUSY_START_RANGE) \
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&& (x <= H_LONG_BUSY_END_RANGE))
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/* Flags */
|
||||
#define H_LARGE_PAGE (1ULL<<(63-16))
|
||||
#define H_EXACT (1ULL<<(63-24)) /* Use exact PTE or return H_PTEG_FULL */
|
||||
#define H_R_XLATE (1ULL<<(63-25)) /* include a valid logical page num in the pte if the valid bit is set */
|
||||
#define H_READ_4 (1ULL<<(63-26)) /* Return 4 PTEs */
|
||||
#define H_PAGE_STATE_CHANGE (1ULL<<(63-28))
|
||||
#define H_PAGE_UNUSED ((1ULL<<(63-29)) | (1ULL<<(63-30)))
|
||||
#define H_PAGE_SET_UNUSED (H_PAGE_STATE_CHANGE | H_PAGE_UNUSED)
|
||||
#define H_PAGE_SET_LOANED (H_PAGE_SET_UNUSED | (1ULL<<(63-31)))
|
||||
#define H_PAGE_SET_ACTIVE H_PAGE_STATE_CHANGE
|
||||
#define H_AVPN (1ULL<<(63-32)) /* An avpn is provided as a sanity test */
|
||||
#define H_ANDCOND (1ULL<<(63-33))
|
||||
#define H_ICACHE_INVALIDATE (1ULL<<(63-40)) /* icbi, etc. (ignored for IO pages) */
|
||||
#define H_ICACHE_SYNCHRONIZE (1ULL<<(63-41)) /* dcbst, icbi, etc (ignored for IO pages */
|
||||
#define H_ZERO_PAGE (1ULL<<(63-48)) /* zero the page before mapping (ignored for IO pages) */
|
||||
#define H_COPY_PAGE (1ULL<<(63-49))
|
||||
#define H_N (1ULL<<(63-61))
|
||||
#define H_PP1 (1ULL<<(63-62))
|
||||
#define H_PP2 (1ULL<<(63-63))
|
||||
|
||||
/* VASI States */
|
||||
#define H_VASI_INVALID 0
|
||||
#define H_VASI_ENABLED 1
|
||||
#define H_VASI_ABORTED 2
|
||||
#define H_VASI_SUSPENDING 3
|
||||
#define H_VASI_SUSPENDED 4
|
||||
#define H_VASI_RESUMED 5
|
||||
#define H_VASI_COMPLETED 6
|
||||
|
||||
/* DABRX flags */
|
||||
#define H_DABRX_HYPERVISOR (1ULL<<(63-61))
|
||||
#define H_DABRX_KERNEL (1ULL<<(63-62))
|
||||
#define H_DABRX_USER (1ULL<<(63-63))
|
||||
|
||||
/* Each control block has to be on a 4K bondary */
|
||||
#define H_CB_ALIGNMENT 4096
|
||||
|
||||
/* pSeries hypervisor opcodes */
|
||||
#define H_REMOVE 0x04
|
||||
#define H_ENTER 0x08
|
||||
#define H_READ 0x0c
|
||||
#define H_CLEAR_MOD 0x10
|
||||
#define H_CLEAR_REF 0x14
|
||||
#define H_PROTECT 0x18
|
||||
#define H_GET_TCE 0x1c
|
||||
#define H_PUT_TCE 0x20
|
||||
#define H_SET_SPRG0 0x24
|
||||
#define H_SET_DABR 0x28
|
||||
#define H_PAGE_INIT 0x2c
|
||||
#define H_SET_ASR 0x30
|
||||
#define H_ASR_ON 0x34
|
||||
#define H_ASR_OFF 0x38
|
||||
#define H_LOGICAL_CI_LOAD 0x3c
|
||||
#define H_LOGICAL_CI_STORE 0x40
|
||||
#define H_LOGICAL_CACHE_LOAD 0x44
|
||||
#define H_LOGICAL_CACHE_STORE 0x48
|
||||
#define H_LOGICAL_ICBI 0x4c
|
||||
#define H_LOGICAL_DCBF 0x50
|
||||
#define H_GET_TERM_CHAR 0x54
|
||||
#define H_PUT_TERM_CHAR 0x58
|
||||
#define H_REAL_TO_LOGICAL 0x5c
|
||||
#define H_HYPERVISOR_DATA 0x60
|
||||
#define H_EOI 0x64
|
||||
#define H_CPPR 0x68
|
||||
#define H_IPI 0x6c
|
||||
#define H_IPOLL 0x70
|
||||
#define H_XIRR 0x74
|
||||
#define H_PERFMON 0x7c
|
||||
#define H_MIGRATE_DMA 0x78
|
||||
#define H_REGISTER_VPA 0xDC
|
||||
#define H_CEDE 0xE0
|
||||
#define H_CONFER 0xE4
|
||||
#define H_PROD 0xE8
|
||||
#define H_GET_PPP 0xEC
|
||||
#define H_SET_PPP 0xF0
|
||||
#define H_PURR 0xF4
|
||||
#define H_PIC 0xF8
|
||||
#define H_REG_CRQ 0xFC
|
||||
#define H_FREE_CRQ 0x100
|
||||
#define H_VIO_SIGNAL 0x104
|
||||
#define H_SEND_CRQ 0x108
|
||||
#define H_COPY_RDMA 0x110
|
||||
#define H_REGISTER_LOGICAL_LAN 0x114
|
||||
#define H_FREE_LOGICAL_LAN 0x118
|
||||
#define H_ADD_LOGICAL_LAN_BUFFER 0x11C
|
||||
#define H_SEND_LOGICAL_LAN 0x120
|
||||
#define H_BULK_REMOVE 0x124
|
||||
#define H_MULTICAST_CTRL 0x130
|
||||
#define H_SET_XDABR 0x134
|
||||
#define H_STUFF_TCE 0x138
|
||||
#define H_PUT_TCE_INDIRECT 0x13C
|
||||
#define H_CHANGE_LOGICAL_LAN_MAC 0x14C
|
||||
#define H_VTERM_PARTNER_INFO 0x150
|
||||
#define H_REGISTER_VTERM 0x154
|
||||
#define H_FREE_VTERM 0x158
|
||||
#define H_RESET_EVENTS 0x15C
|
||||
#define H_ALLOC_RESOURCE 0x160
|
||||
#define H_FREE_RESOURCE 0x164
|
||||
#define H_MODIFY_QP 0x168
|
||||
#define H_QUERY_QP 0x16C
|
||||
#define H_REREGISTER_PMR 0x170
|
||||
#define H_REGISTER_SMR 0x174
|
||||
#define H_QUERY_MR 0x178
|
||||
#define H_QUERY_MW 0x17C
|
||||
#define H_QUERY_HCA 0x180
|
||||
#define H_QUERY_PORT 0x184
|
||||
#define H_MODIFY_PORT 0x188
|
||||
#define H_DEFINE_AQP1 0x18C
|
||||
#define H_GET_TRACE_BUFFER 0x190
|
||||
#define H_DEFINE_AQP0 0x194
|
||||
#define H_RESIZE_MR 0x198
|
||||
#define H_ATTACH_MCQP 0x19C
|
||||
#define H_DETACH_MCQP 0x1A0
|
||||
#define H_CREATE_RPT 0x1A4
|
||||
#define H_REMOVE_RPT 0x1A8
|
||||
#define H_REGISTER_RPAGES 0x1AC
|
||||
#define H_DISABLE_AND_GETC 0x1B0
|
||||
#define H_ERROR_DATA 0x1B4
|
||||
#define H_GET_HCA_INFO 0x1B8
|
||||
#define H_GET_PERF_COUNT 0x1BC
|
||||
#define H_MANAGE_TRACE 0x1C0
|
||||
#define H_FREE_LOGICAL_LAN_BUFFER 0x1D4
|
||||
#define H_QUERY_INT_STATE 0x1E4
|
||||
#define H_POLL_PENDING 0x1D8
|
||||
#define H_ILLAN_ATTRIBUTES 0x244
|
||||
#define H_MODIFY_HEA_QP 0x250
|
||||
#define H_QUERY_HEA_QP 0x254
|
||||
#define H_QUERY_HEA 0x258
|
||||
#define H_QUERY_HEA_PORT 0x25C
|
||||
#define H_MODIFY_HEA_PORT 0x260
|
||||
#define H_REG_BCMC 0x264
|
||||
#define H_DEREG_BCMC 0x268
|
||||
#define H_REGISTER_HEA_RPAGES 0x26C
|
||||
#define H_DISABLE_AND_GET_HEA 0x270
|
||||
#define H_GET_HEA_INFO 0x274
|
||||
#define H_ALLOC_HEA_RESOURCE 0x278
|
||||
#define H_ADD_CONN 0x284
|
||||
#define H_DEL_CONN 0x288
|
||||
#define H_JOIN 0x298
|
||||
#define H_VASI_STATE 0x2A4
|
||||
#define H_ENABLE_CRQ 0x2B0
|
||||
#define H_GET_EM_PARMS 0x2B8
|
||||
#define H_SET_MPP 0x2D0
|
||||
#define H_GET_MPP 0x2D4
|
||||
#define MAX_HCALL_OPCODE H_GET_MPP
|
||||
|
||||
extern sPAPREnvironment *spapr;
|
||||
|
||||
/*#define DEBUG_SPAPR_HCALLS*/
|
||||
|
||||
#ifdef DEBUG_SPAPR_HCALLS
|
||||
#define hcall_dprintf(fmt, ...) \
|
||||
do { fprintf(stderr, fmt, ## __VA_ARGS__); } while (0)
|
||||
#else
|
||||
#define hcall_dprintf(fmt, ...) \
|
||||
do { } while (0)
|
||||
#endif
|
||||
|
||||
typedef target_ulong (*spapr_hcall_fn)(CPUState *env, sPAPREnvironment *spapr,
|
||||
target_ulong opcode,
|
||||
target_ulong *args);
|
||||
|
||||
void spapr_register_hypercall(target_ulong opcode, spapr_hcall_fn fn);
|
||||
target_ulong spapr_hypercall(CPUState *env, target_ulong opcode,
|
||||
target_ulong *args);
|
||||
|
||||
#endif /* !defined (__HW_SPAPR_H__) */
|
||||
|
|
@ -0,0 +1,41 @@
|
|||
#include "sysemu.h"
|
||||
#include "cpu.h"
|
||||
#include "qemu-char.h"
|
||||
#include "hw/spapr.h"
|
||||
|
||||
spapr_hcall_fn hypercall_table[(MAX_HCALL_OPCODE / 4) + 1];
|
||||
|
||||
void spapr_register_hypercall(target_ulong opcode, spapr_hcall_fn fn)
|
||||
{
|
||||
spapr_hcall_fn old_fn;
|
||||
|
||||
assert(opcode <= MAX_HCALL_OPCODE);
|
||||
assert((opcode & 0x3) == 0);
|
||||
|
||||
old_fn = hypercall_table[opcode / 4];
|
||||
|
||||
assert(!old_fn || (fn == old_fn));
|
||||
|
||||
hypercall_table[opcode / 4] = fn;
|
||||
}
|
||||
|
||||
target_ulong spapr_hypercall(CPUState *env, target_ulong opcode,
|
||||
target_ulong *args)
|
||||
{
|
||||
if (msr_pr) {
|
||||
hcall_dprintf("Hypercall made with MSR[PR]=1\n");
|
||||
return H_PRIVILEGE;
|
||||
}
|
||||
|
||||
if ((opcode <= MAX_HCALL_OPCODE)
|
||||
&& ((opcode & 0x3) == 0)) {
|
||||
spapr_hcall_fn fn = hypercall_table[opcode / 4];
|
||||
|
||||
if (fn) {
|
||||
return fn(env, spapr, opcode, args);
|
||||
}
|
||||
}
|
||||
|
||||
hcall_dprintf("Unimplemented hcall 0x" TARGET_FMT_lx "\n", opcode);
|
||||
return H_FUNCTION;
|
||||
}
|
||||
Loading…
Reference in New Issue