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target/arm: Convert Neon 3-reg-same VQRDMLAH/VQRDMLSH to decodetree 

Convert the Neon VQRDMLAH and VQRDMLSH insns in the 3-reg-same group
to decodetree.  These don't use do_3same() because they want to
operate on VFP double registers, whose offsets are different from the
neon_reg_offset() calculations do_3same does.

Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
Reviewed-by: Richard Henderson <richard.henderson@linaro.org>
Message-id: 20200512163904.10918-2-peter.maydell@linaro.org
This commit is contained in:
Peter Maydell 2020-05-12 17:38:48 +01:00
parent f7e462f82b
commit a063569508
3 changed files with 20 additions and 12 deletions
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3
target/arm/neon-dp.decode
View File

@ -97,3 +97,6 @@ VMLS_3s 1111 001 1 0 . .. .... .... 1001 . . . 0 .... @3same
VMUL_3s 1111 001 0 0 . .. .... .... 1001 . . . 1 .... @3same
VMUL_p_3s 1111 001 1 0 . .. .... .... 1001 . . . 1 .... @3same
VQRDMLAH_3s 1111 001 1 0 . .. .... .... 1011 ... 1 .... @3same
VQRDMLSH_3s 1111 001 1 0 . .. .... .... 1100 ... 1 .... @3same

15
target/arm/translate-neon.inc.c
View File

@ -671,3 +671,18 @@ static bool trans_VMUL_p_3s(DisasContext *s, arg_3same *a)
}
return do_3same(s, a, gen_VMUL_p_3s);
}
#define DO_VQRDMLAH(INSN, FUNC) \
static bool trans_##INSN##_3s(DisasContext *s, arg_3same *a) \
{ \
if (!dc_isar_feature(aa32_rdm, s)) { \
return false; \
} \
if (a->size != 1 && a->size != 2) { \
return false; \
} \
return do_3same(s, a, FUNC); \
}
DO_VQRDMLAH(VQRDMLAH, gen_gvec_sqrdmlah_qc)
DO_VQRDMLAH(VQRDMLSH, gen_gvec_sqrdmlsh_qc)

14
target/arm/translate.c
View File

@ -5450,12 +5450,7 @@ static int disas_neon_data_insn(DisasContext *s, uint32_t insn)
if (!u) {
break; /* VPADD */
}
/* VQRDMLAH */
if (dc_isar_feature(aa32_rdm, s) && (size == 1 || size == 2)) {
gen_gvec_sqrdmlah_qc(size, rd_ofs, rn_ofs, rm_ofs,
vec_size, vec_size);
return 0;
}
/* VQRDMLAH : handled by decodetree */
return 1;
case NEON_3R_VFM_VQRDMLSH:
@ -5466,12 +5461,7 @@ static int disas_neon_data_insn(DisasContext *s, uint32_t insn)
}
break;
}
/* VQRDMLSH */
if (dc_isar_feature(aa32_rdm, s) && (size == 1 || size == 2)) {
gen_gvec_sqrdmlsh_qc(size, rd_ofs, rn_ofs, rm_ofs,
vec_size, vec_size);
return 0;
}
/* VQRDMLSH : handled by decodetree */
return 1;
case NEON_3R_VABD: