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target-arm: Rename check_s2_startlevel to check_s2_mmu_setup 

Rename check_s2_startlevel to check_s2_mmu_setup in preparation
for additional checks.

Signed-off-by: Edgar E. Iglesias <edgar.iglesias@xilinx.com>
Reviewed-by: Alex Bennée <alex.bennee@linaro.org>
Message-id: 1453932970-14576-3-git-send-email-edgar.iglesias@gmail.com
Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
This commit is contained in:
Edgar E. Iglesias 2016-02-03 13:46:33 +00:00 committed by Peter Maydell
parent 98d68ec289
commit a0e966c93a
1 changed files with 6 additions and 6 deletions
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12
target-arm/helper.c
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@ -6763,17 +6763,18 @@ typedef enum {
} MMUFaultType; } MMUFaultType;
/* /*
* check_s2_startlevel * check_s2_mmu_setup
* @cpu: ARMCPU * @cpu: ARMCPU
* @is_aa64: True if the translation regime is in AArch64 state * @is_aa64: True if the translation regime is in AArch64 state
* @startlevel: Suggested starting level * @startlevel: Suggested starting level
* @inputsize: Bitsize of IPAs * @inputsize: Bitsize of IPAs
* @stride: Page-table stride (See the ARM ARM) * @stride: Page-table stride (See the ARM ARM)
* *
* Returns true if the suggested starting level is OK and false otherwise. * Returns true if the suggested S2 translation parameters are OK and
* false otherwise.
*/ */
static bool check_s2_startlevel(ARMCPU *cpu, bool is_aa64, int level, static bool check_s2_mmu_setup(ARMCPU *cpu, bool is_aa64, int level,
int inputsize, int stride) int inputsize, int stride)
{ {
const int grainsize = stride + 3; const int grainsize = stride + 3;
int startsizecheck; int startsizecheck;
@ -7013,8 +7014,7 @@ static bool get_phys_addr_lpae(CPUARMState *env, target_ulong address,
} }
/* Check that the starting level is valid. */ /* Check that the starting level is valid. */
ok = check_s2_startlevel(cpu, va_size == 64, level, ok = check_s2_mmu_setup(cpu, va_size == 64, level, inputsize, stride);
inputsize, stride);
if (!ok) { if (!ok) {
/* AArch64 reports these as level 0 faults. /* AArch64 reports these as level 0 faults.
* AArch32 reports these as level 1 faults. * AArch32 reports these as level 1 faults.