mirror of https://gitee.com/openkylin/qemu.git
change ID to CLGD5446 - added solidfill support - fixed hidden dac access
git-svn-id: svn://svn.savannah.nongnu.org/qemu/trunk@899 c046a42c-6fe2-441c-8c8c-71466251a162
This commit is contained in:
bellard
parent
aeb3c85f59
commit
a21ae81d8a
278
hw/cirrus_vga.c
278
hw/cirrus_vga.c
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@ -30,6 +30,7 @@
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#include "vga_int.h"
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//#define DEBUG_CIRRUS
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//#define DEBUG_BITBLT
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/***************************************
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*
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@ -46,8 +47,14 @@
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#define CIRRUS_ID_CLGD5428 (0x26<<2)
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#define CIRRUS_ID_CLGD5430 (0x28<<2)
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#define CIRRUS_ID_CLGD5434 (0x2A<<2)
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#define CIRRUS_ID_CLGD5436 (0x2B<<2)
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#define CIRRUS_ID_CLGD5446 (0x2E<<2)
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/* this define is used to select the exact CLGD implementation we
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emulate. */
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//#define CIRRUS_ID CIRRUS_ID_CLGD5430
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#define CIRRUS_ID CIRRUS_ID_CLGD5446
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// sequencer 0x07
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#define CIRRUS_SR7_BPP_VGA 0x00
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#define CIRRUS_SR7_BPP_SVGA 0x01
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@ -120,6 +127,9 @@
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#define CIRRUS_ROP_NOTSRC_OR_DST 0xd6
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#define CIRRUS_ROP_NOTSRC_AND_NOTDST 0xda
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// control 0x33
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#define CIRRUS_BLTMODEEXT_SOLIDFILL 0x04
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// memory-mapped IO
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#define CIRRUS_MMIO_BLTBGCOLOR 0x00 // dword
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#define CIRRUS_MMIO_BLTFGCOLOR 0x04 // dword
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@ -153,12 +163,10 @@
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// PCI 0x00: vendor, 0x02: device
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#define PCI_VENDOR_CIRRUS 0x1013
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#define PCI_DEVICE_CLGD5430 0x00a0 // CLGD5430 or CLGD5440
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#define PCI_DEVICE_CLGD5434 0x00a8
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#define PCI_DEVICE_CLGD5436 0x00ac
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#define PCI_DEVICE_CLGD5446 0x00b8
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#define PCI_DEVICE_ID CIRRUS_ID
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#define PCI_DEVICE_CLGD5462 0x00d0
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#define PCI_DEVICE_CLGD5465 0x00d6
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// PCI 0x04: command(word), 0x06(word): status
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#define PCI_COMMAND_IOACCESS 0x0001
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#define PCI_COMMAND_MEMACCESS 0x0002
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@ -195,7 +203,7 @@
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// PCI 0x38: reserved
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// PCI 0x3c: 0x3c=int-line, 0x3d=int-pin, 0x3e=min-gnt, 0x3f=maax-lat
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#define CIRRUS_PNPMMIO_SIZE 0x800
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#define CIRRUS_PNPMMIO_SIZE 0x1000
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/* I/O and memory hook */
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@ -264,7 +272,7 @@ static void cirrus_bitblt_reset(CirrusVGAState * s);
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*
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***************************************/
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#define IMPLEMENT_FORWARD_BITBLT(name,opline) \
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#define IMPLEMENT_BITBLT(name,opline) \
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static void \
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cirrus_bitblt_rop_fwd_##name( \
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uint8_t *dst,const uint8_t *src, \
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@ -283,9 +291,8 @@ static void cirrus_bitblt_reset(CirrusVGAState * s);
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dst += dstpitch; \
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src += srcpitch; \
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} \
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}
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#define IMPLEMENT_BACKWARD_BITBLT(name,opline) \
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} \
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\
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static void \
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cirrus_bitblt_rop_bkwd_##name( \
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uint8_t *dst,const uint8_t *src, \
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@ -306,39 +313,22 @@ static void cirrus_bitblt_reset(CirrusVGAState * s);
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} \
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}
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IMPLEMENT_FORWARD_BITBLT(0, *dst = 0)
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IMPLEMENT_FORWARD_BITBLT(src_and_dst, *dst = (*src) & (*dst))
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IMPLEMENT_FORWARD_BITBLT(nop, (void) 0)
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IMPLEMENT_FORWARD_BITBLT(src_and_notdst, *dst = (*src) & (~(*dst)))
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IMPLEMENT_FORWARD_BITBLT(notdst, *dst = ~(*dst))
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IMPLEMENT_FORWARD_BITBLT(src, *dst = *src)
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IMPLEMENT_FORWARD_BITBLT(1, *dst = 0xff)
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IMPLEMENT_FORWARD_BITBLT(notsrc_and_dst, *dst = (~(*src)) & (*dst))
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IMPLEMENT_FORWARD_BITBLT(src_xor_dst, *dst = (*src) ^ (*dst))
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IMPLEMENT_FORWARD_BITBLT(src_or_dst, *dst = (*src) | (*dst))
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IMPLEMENT_FORWARD_BITBLT(notsrc_or_notdst, *dst = (~(*src)) | (~(*dst)))
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IMPLEMENT_FORWARD_BITBLT(src_notxor_dst, *dst = ~((*src) ^ (*dst)))
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IMPLEMENT_FORWARD_BITBLT(src_or_notdst, *dst = (*src) | (~(*dst)))
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IMPLEMENT_FORWARD_BITBLT(notsrc, *dst = (~(*src)))
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IMPLEMENT_FORWARD_BITBLT(notsrc_or_dst, *dst = (~(*src)) | (*dst))
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IMPLEMENT_FORWARD_BITBLT(notsrc_and_notdst, *dst = (~(*src)) & (~(*dst)))
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IMPLEMENT_BACKWARD_BITBLT(0, *dst = 0)
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IMPLEMENT_BACKWARD_BITBLT(src_and_dst, *dst = (*src) & (*dst))
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IMPLEMENT_BACKWARD_BITBLT(nop, (void) 0)
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IMPLEMENT_BACKWARD_BITBLT(src_and_notdst, *dst = (*src) & (~(*dst)))
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IMPLEMENT_BACKWARD_BITBLT(notdst, *dst = ~(*dst))
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IMPLEMENT_BACKWARD_BITBLT(src, *dst = *src)
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IMPLEMENT_BACKWARD_BITBLT(1, *dst = 0xff)
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IMPLEMENT_BACKWARD_BITBLT(notsrc_and_dst, *dst = (~(*src)) & (*dst))
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IMPLEMENT_BACKWARD_BITBLT(src_xor_dst, *dst = (*src) ^ (*dst))
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IMPLEMENT_BACKWARD_BITBLT(src_or_dst, *dst = (*src) | (*dst))
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IMPLEMENT_BACKWARD_BITBLT(notsrc_or_notdst, *dst = (~(*src)) | (~(*dst)))
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IMPLEMENT_BACKWARD_BITBLT(src_notxor_dst, *dst = ~((*src) ^ (*dst)))
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IMPLEMENT_BACKWARD_BITBLT(src_or_notdst, *dst = (*src) | (~(*dst)))
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IMPLEMENT_BACKWARD_BITBLT(notsrc, *dst = (~(*src)))
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IMPLEMENT_BACKWARD_BITBLT(notsrc_or_dst, *dst = (~(*src)) | (*dst))
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IMPLEMENT_BACKWARD_BITBLT(notsrc_and_notdst, *dst = (~(*src)) & (~(*dst)))
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IMPLEMENT_BITBLT(0, *dst = 0)
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IMPLEMENT_BITBLT(src_and_dst, *dst = (*src) & (*dst))
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IMPLEMENT_BITBLT(nop, (void) 0)
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IMPLEMENT_BITBLT(src_and_notdst, *dst = (*src) & (~(*dst)))
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IMPLEMENT_BITBLT(notdst, *dst = ~(*dst))
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IMPLEMENT_BITBLT(src, *dst = *src)
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IMPLEMENT_BITBLT(1, *dst = 0xff)
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IMPLEMENT_BITBLT(notsrc_and_dst, *dst = (~(*src)) & (*dst))
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IMPLEMENT_BITBLT(src_xor_dst, *dst = (*src) ^ (*dst))
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IMPLEMENT_BITBLT(src_or_dst, *dst = (*src) | (*dst))
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IMPLEMENT_BITBLT(notsrc_or_notdst, *dst = (~(*src)) | (~(*dst)))
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IMPLEMENT_BITBLT(src_notxor_dst, *dst = ~((*src) ^ (*dst)))
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IMPLEMENT_BITBLT(src_or_notdst, *dst = (*src) | (~(*dst)))
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IMPLEMENT_BITBLT(notsrc, *dst = (~(*src)))
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IMPLEMENT_BITBLT(notsrc_or_dst, *dst = (~(*src)) | (*dst))
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IMPLEMENT_BITBLT(notsrc_and_notdst, *dst = (~(*src)) & (~(*dst)))
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static cirrus_bitblt_rop_t cirrus_get_fwd_rop_handler(uint8_t rop)
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{
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@ -666,7 +656,7 @@ static int cirrus_bitblt_common_patterncopy(CirrusVGAState * s,
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#endif
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return 0;
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}
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dst = s->vram_ptr + s->cirrus_blt_dstaddr;
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for (y = 0; y < s->cirrus_blt_height; y += 8) {
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dstc = dst;
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@ -686,6 +676,120 @@ static int cirrus_bitblt_common_patterncopy(CirrusVGAState * s,
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return 1;
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}
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/* fill */
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static void cirrus_fill_8(CirrusVGAState *s,
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uint8_t *dst, int dst_pitch, int width, int height)
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{
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uint8_t *d, *d1;
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uint32_t val;
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int x, y;
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val = s->cirrus_shadow_gr1;
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d1 = dst;
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for(y = 0; y < height; y++) {
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d = d1;
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for(x = 0; x < width; x++) {
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*d++ = val;
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}
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d1 += dst_pitch;
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}
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}
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static void cirrus_fill_16(CirrusVGAState *s,
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uint8_t *dst, int dst_pitch, int width, int height)
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{
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uint8_t *d, *d1;
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uint32_t val;
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int x, y;
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val = s->cirrus_shadow_gr1 | (s->gr[0x11] << 8);
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val = le16_to_cpu(val);
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width >>= 1;
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d1 = dst;
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for(y = 0; y < height; y++) {
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d = d1;
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for(x = 0; x < width; x++) {
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((uint16_t *)d)[0] = val;
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d += 2;
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}
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d1 += dst_pitch;
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}
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}
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static void cirrus_fill_24(CirrusVGAState *s,
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uint8_t *dst, int dst_pitch, int width, int height)
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{
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uint8_t *d, *d1;
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int x, y;
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d1 = dst;
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for(y = 0; y < height; y++) {
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d = d1;
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for(x = 0; x < width; x += 3) {
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*d++ = s->cirrus_shadow_gr1;
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*d++ = s->gr[0x11];
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*d++ = s->gr[0x13];
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}
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d1 += dst_pitch;
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}
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}
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static void cirrus_fill_32(CirrusVGAState *s,
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uint8_t *dst, int dst_pitch, int width, int height)
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{
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uint8_t *d, *d1;
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uint32_t val;
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int x, y;
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val = s->cirrus_shadow_gr1 | (s->gr[0x11] << 8) |
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(s->gr[0x13] << 8) | (s->gr[0x15] << 8);
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val = le32_to_cpu(val);
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width >>= 2;
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d1 = dst;
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for(y = 0; y < height; y++) {
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d = d1;
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for(x = 0; x < width; x++) {
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((uint32_t *)d)[0] = val;
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d += 4;
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}
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d1 += dst_pitch;
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}
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}
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static int cirrus_bitblt_solidfill(CirrusVGAState *s)
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{
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uint8_t *dst;
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dst = s->vram_ptr + s->cirrus_blt_dstaddr;
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switch (s->cirrus_blt_pixelwidth) {
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case 1:
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cirrus_fill_8(s, dst, s->cirrus_blt_dstpitch,
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s->cirrus_blt_width, s->cirrus_blt_height);
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break;
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case 2:
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cirrus_fill_16(s, dst, s->cirrus_blt_dstpitch,
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s->cirrus_blt_width, s->cirrus_blt_height);
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break;
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case 3:
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cirrus_fill_24(s, dst, s->cirrus_blt_dstpitch,
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s->cirrus_blt_width, s->cirrus_blt_height);
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break;
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default:
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case 4:
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cirrus_fill_32(s, dst, s->cirrus_blt_dstpitch,
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s->cirrus_blt_width, s->cirrus_blt_height);
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break;
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}
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cirrus_invalidate_region(s, s->cirrus_blt_dstaddr,
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s->cirrus_blt_dstpitch, s->cirrus_blt_width,
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s->cirrus_blt_height);
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cirrus_bitblt_reset(s);
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return 1;
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}
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/***************************************
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*
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* bitblt (video-to-video)
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@ -952,6 +1056,19 @@ static void cirrus_bitblt_start(CirrusVGAState * s)
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s->cirrus_blt_mode = s->gr[0x30];
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blt_rop = s->gr[0x32];
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#ifdef DEBUG_BITBLT
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printf("rop=%02x mode=%02x modeext=%02x w=%d h=%d dpitch=%d spicth=%d daddr=%08x saddr=%08x\n",
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blt_rop,
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s->cirrus_blt_mode,
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s->gr[0x33],
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s->cirrus_blt_width,
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s->cirrus_blt_height,
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s->cirrus_blt_dstpitch,
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s->cirrus_blt_srcpitch,
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s->cirrus_blt_dstaddr,
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s->cirrus_blt_srcaddr);
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#endif
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switch (s->cirrus_blt_mode & CIRRUS_BLTMODE_PIXELWIDTHMASK) {
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case CIRRUS_BLTMODE_PIXELWIDTH8:
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s->cirrus_blt_pixelwidth = 1;
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@ -983,26 +1100,34 @@ static void cirrus_bitblt_start(CirrusVGAState * s)
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goto bitblt_ignore;
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}
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if (s->cirrus_blt_mode & CIRRUS_BLTMODE_BACKWARDS) {
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s->cirrus_blt_dstpitch = -s->cirrus_blt_dstpitch;
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s->cirrus_blt_srcpitch = -s->cirrus_blt_srcpitch;
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s->cirrus_rop = cirrus_get_bkwd_rop_handler(blt_rop);
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if ((s->gr[0x33] & CIRRUS_BLTMODEEXT_SOLIDFILL) &&
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(s->cirrus_blt_mode & (CIRRUS_BLTMODE_MEMSYSDEST |
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CIRRUS_BLTMODE_TRANSPARENTCOMP |
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CIRRUS_BLTMODE_PATTERNCOPY |
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CIRRUS_BLTMODE_COLOREXPAND)) ==
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(CIRRUS_BLTMODE_PATTERNCOPY | CIRRUS_BLTMODE_COLOREXPAND)) {
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cirrus_bitblt_solidfill(s);
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} else {
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s->cirrus_rop = cirrus_get_fwd_rop_handler(blt_rop);
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if (s->cirrus_blt_mode & CIRRUS_BLTMODE_BACKWARDS) {
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s->cirrus_blt_dstpitch = -s->cirrus_blt_dstpitch;
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s->cirrus_blt_srcpitch = -s->cirrus_blt_srcpitch;
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s->cirrus_rop = cirrus_get_bkwd_rop_handler(blt_rop);
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} else {
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s->cirrus_rop = cirrus_get_fwd_rop_handler(blt_rop);
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}
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// setup bitblt engine.
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if (s->cirrus_blt_mode & CIRRUS_BLTMODE_MEMSYSSRC) {
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if (!cirrus_bitblt_cputovideo(s))
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goto bitblt_ignore;
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} else if (s->cirrus_blt_mode & CIRRUS_BLTMODE_MEMSYSDEST) {
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if (!cirrus_bitblt_videotocpu(s))
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goto bitblt_ignore;
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} else {
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if (!cirrus_bitblt_videotovideo(s))
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goto bitblt_ignore;
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}
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}
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// setup bitblt engine.
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if (s->cirrus_blt_mode & CIRRUS_BLTMODE_MEMSYSSRC) {
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if (!cirrus_bitblt_cputovideo(s))
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goto bitblt_ignore;
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} else if (s->cirrus_blt_mode & CIRRUS_BLTMODE_MEMSYSDEST) {
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if (!cirrus_bitblt_videotocpu(s))
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goto bitblt_ignore;
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} else {
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if (!cirrus_bitblt_videotovideo(s))
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goto bitblt_ignore;
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}
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return;
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bitblt_ignore:;
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cirrus_bitblt_reset(s);
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@ -1325,11 +1450,9 @@ cirrus_hook_write_sr(CirrusVGAState * s, unsigned reg_index, int reg_value)
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static void cirrus_read_hidden_dac(CirrusVGAState * s, int *reg_value)
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{
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*reg_value = 0xff;
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if (s->cirrus_hidden_dac_lockindex < 5) {
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if (s->cirrus_hidden_dac_lockindex == 4) {
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*reg_value = s->cirrus_hidden_dac_data;
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}
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s->cirrus_hidden_dac_lockindex++;
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if (++s->cirrus_hidden_dac_lockindex == 5) {
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*reg_value = s->cirrus_hidden_dac_data;
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s->cirrus_hidden_dac_lockindex = 0;
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}
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}
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@ -1337,7 +1460,7 @@ static void cirrus_write_hidden_dac(CirrusVGAState * s, int reg_value)
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{
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if (s->cirrus_hidden_dac_lockindex == 4) {
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s->cirrus_hidden_dac_data = reg_value;
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#ifdef DEBUG_CIRRUS
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#if defined(DEBUG_CIRRUS)
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printf("cirrus: outport hidden DAC, value %02x\n", reg_value);
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#endif
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}
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@ -1468,6 +1591,7 @@ cirrus_hook_write_gr(CirrusVGAState * s, unsigned reg_index, int reg_value)
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case 0x2d: // BLT SRC ADDR 0x00ff00
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case 0x30: // BLT MODE
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case 0x32: // RASTER OP
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case 0x33: // BLT MODEEXT
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case 0x34: // BLT TRANSPARENT COLOR 0x00ff
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case 0x35: // BLT TRANSPARENT COLOR 0xff00
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case 0x38: // BLT TRANSPARENT COLOR MASK 0x00ff
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@ -1703,6 +1827,9 @@ static uint8_t cirrus_mmio_blt_read(CirrusVGAState * s, unsigned address)
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case CIRRUS_MMIO_BLTROP:
|
||||
cirrus_hook_read_gr(s, 0x32, &value);
|
||||
break;
|
||||
case CIRRUS_MMIO_BLTMODEEXT:
|
||||
cirrus_hook_read_gr(s, 0x33, &value);
|
||||
break;
|
||||
case (CIRRUS_MMIO_BLTTRANSPARENTCOLOR + 0):
|
||||
cirrus_hook_read_gr(s, 0x34, &value);
|
||||
break;
|
||||
|
|
@ -1810,6 +1937,9 @@ static void cirrus_mmio_blt_write(CirrusVGAState * s, unsigned address,
|
|||
case CIRRUS_MMIO_BLTROP:
|
||||
cirrus_hook_write_gr(s, 0x32, value);
|
||||
break;
|
||||
case CIRRUS_MMIO_BLTMODEEXT:
|
||||
cirrus_hook_write_gr(s, 0x33, value);
|
||||
break;
|
||||
case (CIRRUS_MMIO_BLTTRANSPARENTCOLOR + 0):
|
||||
cirrus_hook_write_gr(s, 0x34, value);
|
||||
break;
|
||||
|
|
@ -2592,7 +2722,7 @@ static void cirrus_init_common(CirrusVGAState * s)
|
|||
s->sr[0x0F] = CIRRUS_MEMSIZE_2M;
|
||||
s->sr[0x1F] = 0x22; // MemClock
|
||||
|
||||
s->cr[0x27] = CIRRUS_ID_CLGD5430;
|
||||
s->cr[0x27] = CIRRUS_ID;
|
||||
|
||||
s->cirrus_hidden_dac_lockindex = 5;
|
||||
s->cirrus_hidden_dac_data = 0;
|
||||
|
|
@ -2670,8 +2800,8 @@ void pci_cirrus_vga_init(DisplayState *ds, uint8_t *vga_ram_base,
|
|||
pci_conf = d->dev.config;
|
||||
pci_conf[0x00] = (uint8_t) (PCI_VENDOR_CIRRUS & 0xff);
|
||||
pci_conf[0x01] = (uint8_t) (PCI_VENDOR_CIRRUS >> 8);
|
||||
pci_conf[0x02] = (uint8_t) (PCI_DEVICE_CLGD5430 & 0xff);
|
||||
pci_conf[0x03] = (uint8_t) (PCI_DEVICE_CLGD5430 >> 8);
|
||||
pci_conf[0x02] = (uint8_t) (PCI_DEVICE_ID & 0xff);
|
||||
pci_conf[0x03] = (uint8_t) (PCI_DEVICE_ID >> 8);
|
||||
pci_conf[0x04] = PCI_COMMAND_IOACCESS | PCI_COMMAND_MEMACCESS;
|
||||
pci_conf[0x0a] = PCI_CLASS_SUB_VGA;
|
||||
pci_conf[0x0b] = PCI_CLASS_BASE_DISPLAY;
|
||||
|
|
@ -2689,8 +2819,10 @@ void pci_cirrus_vga_init(DisplayState *ds, uint8_t *vga_ram_base,
|
|||
/* memory #1 memory-mapped I/O */
|
||||
/* XXX: s->vram_size must be a power of two */
|
||||
pci_register_io_region((PCIDevice *)d, 0, s->vram_size,
|
||||
PCI_ADDRESS_SPACE_MEM, cirrus_pci_lfb_map);
|
||||
pci_register_io_region((PCIDevice *)d, 1, CIRRUS_PNPMMIO_SIZE,
|
||||
PCI_ADDRESS_SPACE_MEM, cirrus_pci_mmio_map);
|
||||
PCI_ADDRESS_SPACE_MEM_PREFETCH, cirrus_pci_lfb_map);
|
||||
if (CIRRUS_ID == CIRRUS_ID_CLGD5446) {
|
||||
pci_register_io_region((PCIDevice *)d, 1, CIRRUS_PNPMMIO_SIZE,
|
||||
PCI_ADDRESS_SPACE_MEM, cirrus_pci_mmio_map);
|
||||
}
|
||||
/* XXX: ROM BIOS */
|
||||
}
|
||||
|
|
|
|||
Loading…
Reference in New Issue