mirror of https://gitee.com/openkylin/qemu.git
nios2: Add periodic timer emulation
Add the Altera timer model. Signed-off-by: Marek Vasut <marex@denx.de> Cc: Chris Wulff <crwulff@gmail.com> Cc: Jeff Da Silva <jdasilva@altera.com> Cc: Ley Foon Tan <lftan@altera.com> Cc: Sandra Loosemore <sandra@codesourcery.com> Cc: Yves Vandervennet <yvanderv@altera.com> Reviewed-by: Alexander Graf <agraf@suse.de> Message-Id: <20170118220146.489-6-marex@denx.de> Signed-off-by: Richard Henderson <rth@twiddle.net>
This commit is contained in:
Chris Wulff
Richard Henderson
parent
d2fe4ec19d
commit
a32a225357
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@ -18,6 +18,7 @@ common-obj-$(CONFIG_IMX) += imx_gpt.o
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common-obj-$(CONFIG_LM32) += lm32_timer.o
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common-obj-$(CONFIG_MILKYMIST) += milkymist-sysctl.o
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obj-$(CONFIG_ALTERA_TIMER) += altera_timer.o
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obj-$(CONFIG_EXYNOS4) += exynos4210_mct.o
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obj-$(CONFIG_EXYNOS4) += exynos4210_pwm.o
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obj-$(CONFIG_EXYNOS4) += exynos4210_rtc.o
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@ -0,0 +1,237 @@
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/*
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* QEMU model of the Altera timer.
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*
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* Copyright (c) 2012 Chris Wulff <crwulff@gmail.com>
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*
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* This library is free software; you can redistribute it and/or
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* modify it under the terms of the GNU Lesser General Public
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* License as published by the Free Software Foundation; either
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* version 2.1 of the License, or (at your option) any later version.
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*
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* This library is distributed in the hope that it will be useful,
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* but WITHOUT ANY WARRANTY; without even the implied warranty of
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* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the GNU
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* Lesser General Public License for more details.
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*
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* You should have received a copy of the GNU Lesser General Public
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* License along with this library; if not, see
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* <http://www.gnu.org/licenses/lgpl-2.1.html>
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*/
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#include "qemu/osdep.h"
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#include "qemu-common.h"
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#include "qapi/error.h"
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#include "hw/sysbus.h"
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#include "sysemu/sysemu.h"
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#include "hw/ptimer.h"
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#define R_STATUS 0
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#define R_CONTROL 1
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#define R_PERIODL 2
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#define R_PERIODH 3
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#define R_SNAPL 4
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#define R_SNAPH 5
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#define R_MAX 6
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#define STATUS_TO 0x0001
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#define STATUS_RUN 0x0002
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#define CONTROL_ITO 0x0001
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#define CONTROL_CONT 0x0002
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#define CONTROL_START 0x0004
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#define CONTROL_STOP 0x0008
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#define TYPE_ALTERA_TIMER "ALTR.timer"
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#define ALTERA_TIMER(obj) \
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OBJECT_CHECK(AlteraTimer, (obj), TYPE_ALTERA_TIMER)
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typedef struct AlteraTimer {
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SysBusDevice busdev;
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MemoryRegion mmio;
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qemu_irq irq;
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uint32_t freq_hz;
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QEMUBH *bh;
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ptimer_state *ptimer;
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uint32_t regs[R_MAX];
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} AlteraTimer;
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static int timer_irq_state(AlteraTimer *t)
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{
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bool irq = (t->regs[R_STATUS] & STATUS_TO) &&
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(t->regs[R_CONTROL] & CONTROL_ITO);
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return irq;
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}
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static uint64_t timer_read(void *opaque, hwaddr addr,
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unsigned int size)
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{
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AlteraTimer *t = opaque;
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uint64_t r = 0;
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addr >>= 2;
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switch (addr) {
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case R_CONTROL:
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r = t->regs[R_CONTROL] & (CONTROL_ITO | CONTROL_CONT);
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break;
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default:
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if (addr < ARRAY_SIZE(t->regs)) {
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r = t->regs[addr];
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}
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break;
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}
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return r;
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}
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static void timer_write(void *opaque, hwaddr addr,
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uint64_t value, unsigned int size)
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{
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AlteraTimer *t = opaque;
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uint64_t tvalue;
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uint32_t count = 0;
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int irqState = timer_irq_state(t);
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addr >>= 2;
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switch (addr) {
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case R_STATUS:
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/* The timeout bit is cleared by writing the status register. */
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t->regs[R_STATUS] &= ~STATUS_TO;
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break;
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case R_CONTROL:
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t->regs[R_CONTROL] = value & (CONTROL_ITO | CONTROL_CONT);
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if ((value & CONTROL_START) &&
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!(t->regs[R_STATUS] & STATUS_RUN)) {
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ptimer_run(t->ptimer, 1);
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t->regs[R_STATUS] |= STATUS_RUN;
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}
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if ((value & CONTROL_STOP) && (t->regs[R_STATUS] & STATUS_RUN)) {
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ptimer_stop(t->ptimer);
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t->regs[R_STATUS] &= ~STATUS_RUN;
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}
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break;
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case R_PERIODL:
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case R_PERIODH:
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t->regs[addr] = value & 0xFFFF;
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if (t->regs[R_STATUS] & STATUS_RUN) {
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ptimer_stop(t->ptimer);
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t->regs[R_STATUS] &= ~STATUS_RUN;
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}
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tvalue = (t->regs[R_PERIODH] << 16) | t->regs[R_PERIODL];
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ptimer_set_limit(t->ptimer, tvalue + 1, 1);
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break;
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case R_SNAPL:
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case R_SNAPH:
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count = ptimer_get_count(t->ptimer);
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t->regs[R_SNAPL] = count & 0xFFFF;
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t->regs[R_SNAPH] = count >> 16;
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break;
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default:
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break;
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}
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if (irqState != timer_irq_state(t)) {
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qemu_set_irq(t->irq, timer_irq_state(t));
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}
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}
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static const MemoryRegionOps timer_ops = {
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.read = timer_read,
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.write = timer_write,
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.endianness = DEVICE_NATIVE_ENDIAN,
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.valid = {
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.min_access_size = 1,
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.max_access_size = 4
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}
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};
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static void timer_hit(void *opaque)
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{
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AlteraTimer *t = opaque;
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const uint64_t tvalue = (t->regs[R_PERIODH] << 16) | t->regs[R_PERIODL];
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t->regs[R_STATUS] |= STATUS_TO;
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ptimer_set_limit(t->ptimer, tvalue + 1, 1);
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if (!(t->regs[R_CONTROL] & CONTROL_CONT)) {
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t->regs[R_STATUS] &= ~STATUS_RUN;
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ptimer_set_count(t->ptimer, tvalue);
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} else {
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ptimer_run(t->ptimer, 1);
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}
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qemu_set_irq(t->irq, timer_irq_state(t));
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}
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static void altera_timer_realize(DeviceState *dev, Error **errp)
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{
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AlteraTimer *t = ALTERA_TIMER(dev);
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SysBusDevice *sbd = SYS_BUS_DEVICE(dev);
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if (t->freq_hz == 0) {
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error_setg(errp, "\"clock-frequency\" property must be provided.");
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return;
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}
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t->bh = qemu_bh_new(timer_hit, t);
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t->ptimer = ptimer_init(t->bh, PTIMER_POLICY_DEFAULT);
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ptimer_set_freq(t->ptimer, t->freq_hz);
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memory_region_init_io(&t->mmio, OBJECT(t), &timer_ops, t,
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TYPE_ALTERA_TIMER, R_MAX * sizeof(uint32_t));
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sysbus_init_mmio(sbd, &t->mmio);
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}
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static void altera_timer_init(Object *obj)
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{
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AlteraTimer *t = ALTERA_TIMER(obj);
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SysBusDevice *sbd = SYS_BUS_DEVICE(obj);
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sysbus_init_irq(sbd, &t->irq);
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}
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static void altera_timer_reset(DeviceState *dev)
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{
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AlteraTimer *t = ALTERA_TIMER(dev);
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ptimer_stop(t->ptimer);
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ptimer_set_limit(t->ptimer, 0xffffffff, 1);
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memset(t->regs, 0, ARRAY_SIZE(t->regs));
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}
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static Property altera_timer_properties[] = {
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DEFINE_PROP_UINT32("clock-frequency", AlteraTimer, freq_hz, 0),
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DEFINE_PROP_END_OF_LIST(),
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};
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static void altera_timer_class_init(ObjectClass *klass, void *data)
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{
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DeviceClass *dc = DEVICE_CLASS(klass);
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dc->realize = altera_timer_realize;
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dc->props = altera_timer_properties;
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dc->reset = altera_timer_reset;
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}
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static const TypeInfo altera_timer_info = {
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.name = TYPE_ALTERA_TIMER,
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.parent = TYPE_SYS_BUS_DEVICE,
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.instance_size = sizeof(AlteraTimer),
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.instance_init = altera_timer_init,
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.class_init = altera_timer_class_init,
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};
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static void altera_timer_register(void)
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{
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type_register_static(&altera_timer_info);
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}
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type_init(altera_timer_register)
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