mirror of https://gitee.com/openkylin/qemu.git
explicited S3 specific code - added more debug code
git-svn-id: svn://svn.savannah.nongnu.org/qemu/trunk@497 c046a42c-6fe2-441c-8c8c-71466251a162
This commit is contained in:
bellard
parent
3bfd9da14f
commit
a41bc9af8f
46
hw/vga.c
46
hw/vga.c
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@ -50,6 +50,10 @@
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//#define DEBUG_VGA
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//#define DEBUG_VGA_MEM
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//#define DEBUG_VGA_REG
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//#define DEBUG_S3
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#define CONFIG_S3VGA
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#define MSR_COLOR_EMULATION 0x01
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#define MSR_PAGE_SELECT 0x20
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@ -252,6 +256,9 @@ static uint32_t vga_ioport_read(CPUX86State *env, uint32_t addr)
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break;
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case 0x3c5:
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val = s->sr[s->sr_index];
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#ifdef DEBUG_VGA_REG
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printf("vga: read SR%x = 0x%02x\n", s->sr_index, val);
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#endif
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break;
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case 0x3c7:
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val = s->dac_state;
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@ -274,6 +281,9 @@ static uint32_t vga_ioport_read(CPUX86State *env, uint32_t addr)
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break;
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case 0x3cf:
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val = s->gr[s->gr_index];
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#ifdef DEBUG_VGA_REG
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printf("vga: read GR%x = 0x%02x\n", s->gr_index, val);
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#endif
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break;
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case 0x3b4:
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case 0x3d4:
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@ -282,6 +292,14 @@ static uint32_t vga_ioport_read(CPUX86State *env, uint32_t addr)
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case 0x3b5:
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case 0x3d5:
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val = s->cr[s->cr_index];
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#ifdef DEBUG_VGA_REG
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printf("vga: read CR%x = 0x%02x\n", s->cr_index, val);
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#endif
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#ifdef DEBUG_S3
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if (s->cr_index >= 0x20)
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printf("S3: CR read index=0x%x val=0x%x\n",
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s->cr_index, val);
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#endif
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break;
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case 0x3ba:
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case 0x3da:
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@ -354,6 +372,9 @@ static void vga_ioport_write(CPUX86State *env, uint32_t addr, uint32_t val)
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s->sr_index = val & 7;
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break;
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case 0x3c5:
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#ifdef DEBUG_VGA_REG
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printf("vga: write SR%x = 0x%02x\n", s->sr_index, val);
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#endif
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s->sr[s->sr_index] = val & sr_mask[s->sr_index];
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break;
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case 0x3c7:
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@ -378,6 +399,9 @@ static void vga_ioport_write(CPUX86State *env, uint32_t addr, uint32_t val)
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s->gr_index = val & 0x0f;
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break;
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case 0x3cf:
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#ifdef DEBUG_VGA_REG
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printf("vga: write GR%x = 0x%02x\n", s->gr_index, val);
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#endif
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s->gr[s->gr_index] = val & gr_mask[s->gr_index];
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break;
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case 0x3b4:
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@ -386,6 +410,9 @@ static void vga_ioport_write(CPUX86State *env, uint32_t addr, uint32_t val)
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break;
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case 0x3b5:
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case 0x3d5:
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#ifdef DEBUG_VGA_REG
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printf("vga: write CR%x = 0x%02x\n", s->cr_index, val);
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#endif
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/* handle CR0-7 protection */
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if ((s->cr[11] & 0x80) && s->cr_index <= 7) {
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/* can always write bit 4 of CR7 */
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@ -403,6 +430,7 @@ static void vga_ioport_write(CPUX86State *env, uint32_t addr, uint32_t val)
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s->cr[s->cr_index] = val;
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break;
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#ifdef CONFIG_S3VGA
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/* S3 registers */
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case 0x2d:
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case 0x2e:
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@ -422,10 +450,16 @@ static void vga_ioport_write(CPUX86State *env, uint32_t addr, uint32_t val)
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v = val & 3;
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s->cr[0x69] = (s->cr[69] & ~0x0c) | (v << 2);
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break;
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#endif
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default:
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s->cr[s->cr_index] = val;
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break;
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}
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#ifdef DEBUG_S3
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if (s->cr_index >= 0x20)
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printf("S3: CR write index=0x%x val=0x%x\n",
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s->cr_index, val);
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#endif
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break;
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case 0x3ba:
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case 0x3da:
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@ -507,7 +541,6 @@ static uint32_t vga_mem_readl(uint32_t addr)
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return v;
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}
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/* called for accesses between 0xa0000 and 0xc0000 */
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void vga_mem_writeb(uint32_t addr, uint32_t val)
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{
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@ -588,7 +621,7 @@ void vga_mem_writeb(uint32_t addr, uint32_t val)
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case 3:
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/* rotate */
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b = s->gr[3] & 7;
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val = ((val >> b) | (val << (8 - b)));
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val = (val >> b) | (val << (8 - b));
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bit_mask = s->gr[8] & val;
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val = mask16[s->gr[0]];
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@ -787,15 +820,20 @@ static int update_basic_params(VGAState *s)
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full_update = 0;
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/* compute line_offset in bytes */
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line_offset = s->cr[0x13];
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#ifdef CONFIG_S3VGA
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v = (s->cr[0x51] >> 4) & 3; /* S3 extension */
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if (v == 0)
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v = (s->cr[0x43] >> 2) & 1; /* S3 extension */
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line_offset = s->cr[0x13] | (v << 8);
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line_offset |= (v << 8);
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#endif
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line_offset <<= 3;
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/* starting address */
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start_addr = s->cr[0x0d] | (s->cr[0x0c] << 8);
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#ifdef CONFIG_S3VGA
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start_addr |= (s->cr[0x69] & 0x1f) << 16; /* S3 extension */
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#endif
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/* line compare */
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line_compare = s->cr[0x18] |
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@ -1290,11 +1328,13 @@ void vga_update_display(void)
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void vga_reset(VGAState *s)
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{
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memset(s, 0, sizeof(VGAState));
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#ifdef CONFIG_S3VGA
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/* chip ID for 8c968 */
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s->cr[0x2d] = 0x88;
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s->cr[0x2e] = 0xb0;
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s->cr[0x2f] = 0x01; /* XXX: check revision code */
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s->cr[0x30] = 0xe1;
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#endif
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s->graphic_mode = -1; /* force full update */
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}
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