mirror of https://gitee.com/openkylin/qemu.git
target/openrisc: Implement move to/from FPCSR
Reviewed-by: Stafford Horne <shorne@gmail.com> Signed-off-by: Richard Henderson <richard.henderson@linaro.org>
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2b13b4b93d
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a465772eea
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@ -55,6 +55,7 @@ static void openrisc_cpu_reset(CPUState *s)
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cpu->env.sr = SR_FO | SR_SM;
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cpu->env.sr = SR_FO | SR_SM;
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cpu->env.lock_addr = -1;
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cpu->env.lock_addr = -1;
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s->exception_index = -1;
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s->exception_index = -1;
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cpu_set_fpcsr(&cpu->env, 0);
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#ifndef CONFIG_USER_ONLY
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#ifndef CONFIG_USER_ONLY
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cpu->env.picmr = 0x00000000;
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cpu->env.picmr = 0x00000000;
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@ -413,6 +413,8 @@ static inline void cpu_set_sr(CPUOpenRISCState *env, uint32_t val)
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env->sr = (val & ~(SR_F | SR_CY | SR_OV)) | SR_FO;
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env->sr = (val & ~(SR_F | SR_CY | SR_OV)) | SR_FO;
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}
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}
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void cpu_set_fpcsr(CPUOpenRISCState *env, uint32_t val);
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#define CPU_INTERRUPT_TIMER CPU_INTERRUPT_TGT_INT_0
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#define CPU_INTERRUPT_TIMER CPU_INTERRUPT_TGT_INT_0
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#endif /* OPENRISC_CPU_H */
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#endif /* OPENRISC_CPU_H */
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@ -61,6 +61,19 @@ void HELPER(update_fpcsr)(CPUOpenRISCState *env)
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}
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}
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}
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}
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void cpu_set_fpcsr(CPUOpenRISCState *env, uint32_t val)
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{
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static const int rm_to_sf[] = {
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float_round_nearest_even,
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float_round_to_zero,
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float_round_up,
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float_round_down
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};
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env->fpcsr = val & 0x7ff;
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set_float_rounding_mode(rm_to_sf[extract32(val, 1, 2)], &env->fp_status);
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}
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uint64_t HELPER(itofd)(CPUOpenRISCState *env, uint64_t val)
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uint64_t HELPER(itofd)(CPUOpenRISCState *env, uint64_t val)
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{
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{
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return int64_to_float64(val, &env->fp_status);
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return int64_to_float64(val, &env->fp_status);
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@ -121,10 +121,21 @@ static const VMStateDescription vmstate_env = {
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}
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}
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};
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};
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static int cpu_post_load(void *opaque, int version_id)
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{
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OpenRISCCPU *cpu = opaque;
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CPUOpenRISCState *env = &cpu->env;
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/* Update env->fp_status to match env->fpcsr. */
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cpu_set_fpcsr(env, env->fpcsr);
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return 0;
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}
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const VMStateDescription vmstate_openrisc_cpu = {
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const VMStateDescription vmstate_openrisc_cpu = {
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.name = "cpu",
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.name = "cpu",
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.version_id = 1,
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.version_id = 1,
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.minimum_version_id = 1,
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.minimum_version_id = 1,
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.post_load = cpu_post_load,
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.fields = (VMStateField[]) {
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.fields = (VMStateField[]) {
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VMSTATE_CPU(),
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VMSTATE_CPU(),
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VMSTATE_STRUCT(env, OpenRISCCPU, 1, vmstate_env, CPUOpenRISCState),
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VMSTATE_STRUCT(env, OpenRISCCPU, 1, vmstate_env, CPUOpenRISCState),
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@ -37,8 +37,10 @@ void HELPER(mtspr)(CPUOpenRISCState *env, target_ulong spr, target_ulong rb)
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CPUState *cs = env_cpu(env);
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CPUState *cs = env_cpu(env);
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target_ulong mr;
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target_ulong mr;
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int idx;
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int idx;
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#endif
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switch (spr) {
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switch (spr) {
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#ifndef CONFIG_USER_ONLY
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case TO_SPR(0, 11): /* EVBAR */
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case TO_SPR(0, 11): /* EVBAR */
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env->evbar = rb;
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env->evbar = rb;
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break;
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break;
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@ -179,10 +181,12 @@ void HELPER(mtspr)(CPUOpenRISCState *env, target_ulong spr, target_ulong rb)
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}
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}
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cpu_openrisc_timer_update(cpu);
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cpu_openrisc_timer_update(cpu);
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break;
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break;
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default:
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#endif
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case TO_SPR(0, 20): /* FPCSR */
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cpu_set_fpcsr(env, rb);
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break;
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break;
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}
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}
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#endif
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}
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}
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target_ulong HELPER(mfspr)(CPUOpenRISCState *env, target_ulong rd,
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target_ulong HELPER(mfspr)(CPUOpenRISCState *env, target_ulong rd,
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@ -193,8 +197,10 @@ target_ulong HELPER(mfspr)(CPUOpenRISCState *env, target_ulong rd,
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OpenRISCCPU *cpu = env_archcpu(env);
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OpenRISCCPU *cpu = env_archcpu(env);
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CPUState *cs = env_cpu(env);
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CPUState *cs = env_cpu(env);
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int idx;
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int idx;
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#endif
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switch (spr) {
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switch (spr) {
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#ifndef CONFIG_USER_ONLY
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case TO_SPR(0, 0): /* VR */
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case TO_SPR(0, 0): /* VR */
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return env->vr;
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return env->vr;
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@ -303,12 +309,12 @@ target_ulong HELPER(mfspr)(CPUOpenRISCState *env, target_ulong rd,
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case TO_SPR(10, 1): /* TTCR */
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case TO_SPR(10, 1): /* TTCR */
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cpu_openrisc_count_update(cpu);
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cpu_openrisc_count_update(cpu);
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return cpu_openrisc_count_get(cpu);
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return cpu_openrisc_count_get(cpu);
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default:
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break;
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}
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#endif
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#endif
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case TO_SPR(0, 20): /* FPCSR */
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return env->fpcsr;
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}
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/* for rd is passed in, if rd unchanged, just keep it back. */
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/* for rd is passed in, if rd unchanged, just keep it back. */
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return rd;
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return rd;
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}
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}
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