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remove remaining occurrences AREG[1-9] and TCG_AREG[1-9] 

Signed-off-by: Paolo Bonzini <pbonzini@redhat.com>
Signed-off-by: Aurelien Jarno <aurelien@aurel32.net>
This commit is contained in:
Paolo Bonzini 2010-03-19 11:31:15 +01:00 committed by Aurelien Jarno
parent 7270547fe8
commit a63b5829af
10 changed files with 1 additions and 50 deletions
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26
dyngen-exec.h
View File

@ -50,62 +50,36 @@ extern int printf(const char *, ...);
#if defined(__i386__) #if defined(__i386__)
#define AREG0 "ebp" #define AREG0 "ebp"
#define AREG1 "ebx"
#define AREG2 "esi"
#elif defined(__x86_64__) #elif defined(__x86_64__)
#define AREG0 "r14" #define AREG0 "r14"
#define AREG1 "r15"
#define AREG2 "r12"
#elif defined(_ARCH_PPC) #elif defined(_ARCH_PPC)
#define AREG0 "r27" #define AREG0 "r27"
#define AREG1 "r24"
#define AREG2 "r25"
#elif defined(__arm__) #elif defined(__arm__)
#define AREG0 "r7" #define AREG0 "r7"
#define AREG1 "r4"
#define AREG2 "r5"
#elif defined(__hppa__) #elif defined(__hppa__)
#define AREG0 "r17" #define AREG0 "r17"
#define AREG1 "r14"
#define AREG2 "r15"
#elif defined(__mips__) #elif defined(__mips__)
#define AREG0 "fp" #define AREG0 "fp"
#define AREG1 "s0"
#define AREG2 "s1"
#elif defined(__sparc__) #elif defined(__sparc__)
#ifdef CONFIG_SOLARIS #ifdef CONFIG_SOLARIS
#define AREG0 "g2" #define AREG0 "g2"
#define AREG1 "g3"
#define AREG2 "g4"
#else #else
#ifdef __sparc_v9__ #ifdef __sparc_v9__
#define AREG0 "g5" #define AREG0 "g5"
#define AREG1 "g6"
#define AREG2 "g7"
#else #else
#define AREG0 "g6" #define AREG0 "g6"
#define AREG1 "g1"
#define AREG2 "g2"
#endif #endif
#endif #endif
#elif defined(__s390__) #elif defined(__s390__)
#define AREG0 "r10" #define AREG0 "r10"
#define AREG1 "r7"
#define AREG2 "r8"
#elif defined(__alpha__) #elif defined(__alpha__)
/* Note $15 is the frame pointer, so anything in op-i386.c that would /* Note $15 is the frame pointer, so anything in op-i386.c that would
require a frame pointer, like alloca, would probably loose. */ require a frame pointer, like alloca, would probably loose. */
#define AREG0 "$15" #define AREG0 "$15"
#define AREG1 "$9"
#define AREG2 "$10"
#elif defined(__mc68000) #elif defined(__mc68000)
#define AREG0 "%a5" #define AREG0 "%a5"
#define AREG1 "%a4"
#define AREG2 "%d7"
#elif defined(__ia64__) #elif defined(__ia64__)
#define AREG0 "r7" #define AREG0 "r7"
#define AREG1 "r4"
#define AREG2 "r5"
#else #else
#error unsupported CPU #error unsupported CPU
#endif #endif

2
tcg/arm/tcg-target.h
View File

@ -73,8 +73,6 @@ enum {
enum { enum {
/* Note: must be synced with dyngen-exec.h */ /* Note: must be synced with dyngen-exec.h */
TCG_AREG0 = TCG_REG_R7, TCG_AREG0 = TCG_REG_R7,
TCG_AREG1 = TCG_REG_R4,
TCG_AREG2 = TCG_REG_R5,
}; };
static inline void flush_icache_range(unsigned long start, unsigned long stop) static inline void flush_icache_range(unsigned long start, unsigned long stop)

2
tcg/hppa/tcg-target.h
View File

@ -83,8 +83,6 @@ enum {
/* Note: must be synced with dyngen-exec.h */ /* Note: must be synced with dyngen-exec.h */
#define TCG_AREG0 TCG_REG_R17 #define TCG_AREG0 TCG_REG_R17
#define TCG_AREG1 TCG_REG_R14
#define TCG_AREG2 TCG_REG_R15
static inline void flush_icache_range(unsigned long start, unsigned long stop) static inline void flush_icache_range(unsigned long start, unsigned long stop)
{ {

2
tcg/i386/tcg-target.h
View File

@ -62,8 +62,6 @@ enum {
/* Note: must be synced with dyngen-exec.h */ /* Note: must be synced with dyngen-exec.h */
#define TCG_AREG0 TCG_REG_EBP #define TCG_AREG0 TCG_REG_EBP
#define TCG_AREG1 TCG_REG_EBX
#define TCG_AREG2 TCG_REG_ESI
static inline void flush_icache_range(unsigned long start, unsigned long stop) static inline void flush_icache_range(unsigned long start, unsigned long stop)
{ {

2
tcg/mips/tcg-target.h
View File

@ -95,8 +95,6 @@ enum {
/* Note: must be synced with dyngen-exec.h */ /* Note: must be synced with dyngen-exec.h */
#define TCG_AREG0 TCG_REG_FP #define TCG_AREG0 TCG_REG_FP
#define TCG_AREG1 TCG_REG_S0
#define TCG_AREG2 TCG_REG_S1
#include <sys/cachectl.h> #include <sys/cachectl.h>

2
tcg/ppc/tcg-target.h
View File

@ -91,7 +91,5 @@ enum {
#define TCG_TARGET_HAS_orc_i32 #define TCG_TARGET_HAS_orc_i32
#define TCG_AREG0 TCG_REG_R27 #define TCG_AREG0 TCG_REG_R27
#define TCG_AREG1 TCG_REG_R24
#define TCG_AREG2 TCG_REG_R25
#define TCG_TARGET_HAS_GUEST_BASE #define TCG_TARGET_HAS_GUEST_BASE

2
tcg/ppc64/tcg-target.h
View File

@ -98,7 +98,5 @@ enum {
/* #define TCG_TARGET_HAS_orc_i64 */ /* #define TCG_TARGET_HAS_orc_i64 */
#define TCG_AREG0 TCG_REG_R27 #define TCG_AREG0 TCG_REG_R27
#define TCG_AREG1 TCG_REG_R24
#define TCG_AREG2 TCG_REG_R25
#define TCG_TARGET_HAS_GUEST_BASE #define TCG_TARGET_HAS_GUEST_BASE

3
tcg/s390/tcg-target.h
View File

@ -84,9 +84,6 @@ enum {
enum { enum {
/* Note: must be synced with dyngen-exec.h */ /* Note: must be synced with dyngen-exec.h */
TCG_AREG0 = TCG_REG_R10, TCG_AREG0 = TCG_REG_R10,
TCG_AREG1 = TCG_REG_R7,
TCG_AREG2 = TCG_REG_R8,
TCG_AREG3 = TCG_REG_R9,
}; };
static inline void flush_icache_range(unsigned long start, unsigned long stop) static inline void flush_icache_range(unsigned long start, unsigned long stop)

8
tcg/sparc/tcg-target.h
View File

@ -119,19 +119,13 @@ enum {
#define TCG_TARGET_HAS_orc_i64 #define TCG_TARGET_HAS_orc_i64
#endif #endif
/* Note: must be synced with dyngen-exec.h and Makefile.target */ /* Note: must be synced with dyngen-exec.h */
#ifdef CONFIG_SOLARIS #ifdef CONFIG_SOLARIS
#define TCG_AREG0 TCG_REG_G2 #define TCG_AREG0 TCG_REG_G2
#define TCG_AREG1 TCG_REG_G3
#define TCG_AREG2 TCG_REG_G4
#elif defined(__sparc_v9__) #elif defined(__sparc_v9__)
#define TCG_AREG0 TCG_REG_G5 #define TCG_AREG0 TCG_REG_G5
#define TCG_AREG1 TCG_REG_G6
#define TCG_AREG2 TCG_REG_G7
#else #else
#define TCG_AREG0 TCG_REG_G6 #define TCG_AREG0 TCG_REG_G6
#define TCG_AREG1 TCG_REG_G1
#define TCG_AREG2 TCG_REG_G2
#endif #endif
static inline void flush_icache_range(unsigned long start, unsigned long stop) static inline void flush_icache_range(unsigned long start, unsigned long stop)

2
tcg/x86_64/tcg-target.h
View File

@ -89,8 +89,6 @@ enum {
/* Note: must be synced with dyngen-exec.h */ /* Note: must be synced with dyngen-exec.h */
#define TCG_AREG0 TCG_REG_R14 #define TCG_AREG0 TCG_REG_R14
#define TCG_AREG1 TCG_REG_R15
#define TCG_AREG2 TCG_REG_R12
static inline void flush_icache_range(unsigned long start, unsigned long stop) static inline void flush_icache_range(unsigned long start, unsigned long stop)
{ {