mirror of https://gitee.com/openkylin/qemu.git
libqos: Handle PCI IO de-multiplexing in common code
The PCI IO space (aka PIO, aka legacy IO) and PCI memory space (aka MMIO) are distinct address spaces by the PCI spec (although parts of one might be aliased to parts of the other in some cases). However, qpci_io_read*() and qpci_io_write*() can perform accesses to either space depending on parameter. That's convenient for test case drivers, since there are a fair few devices which can be controlled via either a PIO or MMIO BAR but with an otherwise identical driver. This is implemented by having addresses below 64kiB treated as PIO, and those above treated as MMIO. This works because low addresses in memory space are generally reserved for DMA rather than MMIO. At the moment, this demultiplexing must be handled by each PCI backend (pc and spapr, so far). There's no real reason for this - the current encoding is likely to work for all platforms, and even if it doesn't we can still use a more complex common encoding since the value returned from iomap are semi-opaque. This patch moves the demultiplexing into the common part of the libqos PCI code, with the backends having simpler, separate accessors for PIO and MMIO space. This also means we have a way of explicitly accessing either space if it's necessary for some special case. Signed-off-by: David Gibson <david@gibson.dropbear.id.au> Reviewed-by: Laurent Vivier <lvivier@redhat.com> Reviewed-by: Greg Kurz <groug@kaod.org>
This commit is contained in:
David Gibson
parent
246fc0fb66
commit
a795fc08f2
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@ -36,79 +36,64 @@ typedef struct QPCIBusPC
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uint16_t pci_iohole_alloc;
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} QPCIBusPC;
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static uint8_t qpci_pc_io_readb(QPCIBus *bus, void *addr)
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static uint8_t qpci_pc_pio_readb(QPCIBus *bus, uint32_t addr)
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{
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uintptr_t port = (uintptr_t)addr;
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uint8_t value;
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if (port < 0x10000) {
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value = inb(port);
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} else {
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value = readb(port);
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}
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return value;
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return inb(addr);
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}
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static uint16_t qpci_pc_io_readw(QPCIBus *bus, void *addr)
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static uint8_t qpci_pc_mmio_readb(QPCIBus *bus, uint32_t addr)
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{
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uintptr_t port = (uintptr_t)addr;
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uint16_t value;
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if (port < 0x10000) {
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value = inw(port);
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} else {
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value = readw(port);
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}
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return value;
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return readb(addr);
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}
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static uint32_t qpci_pc_io_readl(QPCIBus *bus, void *addr)
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static void qpci_pc_pio_writeb(QPCIBus *bus, uint32_t addr, uint8_t val)
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{
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uintptr_t port = (uintptr_t)addr;
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uint32_t value;
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if (port < 0x10000) {
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value = inl(port);
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} else {
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value = readl(port);
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}
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return value;
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outb(addr, val);
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}
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static void qpci_pc_io_writeb(QPCIBus *bus, void *addr, uint8_t value)
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static void qpci_pc_mmio_writeb(QPCIBus *bus, uint32_t addr, uint8_t val)
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{
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uintptr_t port = (uintptr_t)addr;
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if (port < 0x10000) {
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outb(port, value);
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} else {
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writeb(port, value);
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}
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writeb(addr, val);
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}
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static void qpci_pc_io_writew(QPCIBus *bus, void *addr, uint16_t value)
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static uint16_t qpci_pc_pio_readw(QPCIBus *bus, uint32_t addr)
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{
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uintptr_t port = (uintptr_t)addr;
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if (port < 0x10000) {
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outw(port, value);
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} else {
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writew(port, value);
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}
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return inw(addr);
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}
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static void qpci_pc_io_writel(QPCIBus *bus, void *addr, uint32_t value)
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static uint16_t qpci_pc_mmio_readw(QPCIBus *bus, uint32_t addr)
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{
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uintptr_t port = (uintptr_t)addr;
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return readw(addr);
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}
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if (port < 0x10000) {
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outl(port, value);
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} else {
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writel(port, value);
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}
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static void qpci_pc_pio_writew(QPCIBus *bus, uint32_t addr, uint16_t val)
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{
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outw(addr, val);
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}
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static void qpci_pc_mmio_writew(QPCIBus *bus, uint32_t addr, uint16_t val)
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{
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writew(addr, val);
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}
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static uint32_t qpci_pc_pio_readl(QPCIBus *bus, uint32_t addr)
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{
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return inl(addr);
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}
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static uint32_t qpci_pc_mmio_readl(QPCIBus *bus, uint32_t addr)
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{
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return readl(addr);
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}
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static void qpci_pc_pio_writel(QPCIBus *bus, uint32_t addr, uint32_t val)
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{
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outl(addr, val);
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}
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static void qpci_pc_mmio_writel(QPCIBus *bus, uint32_t addr, uint32_t val)
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{
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writel(addr, val);
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}
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static uint8_t qpci_pc_config_readb(QPCIBus *bus, int devfn, uint8_t offset)
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@ -218,13 +203,21 @@ QPCIBus *qpci_init_pc(QGuestAllocator *alloc)
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ret = g_malloc(sizeof(*ret));
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ret->bus.io_readb = qpci_pc_io_readb;
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ret->bus.io_readw = qpci_pc_io_readw;
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ret->bus.io_readl = qpci_pc_io_readl;
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ret->bus.pio_readb = qpci_pc_pio_readb;
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ret->bus.pio_readw = qpci_pc_pio_readw;
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ret->bus.pio_readl = qpci_pc_pio_readl;
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ret->bus.io_writeb = qpci_pc_io_writeb;
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ret->bus.io_writew = qpci_pc_io_writew;
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ret->bus.io_writel = qpci_pc_io_writel;
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ret->bus.pio_writeb = qpci_pc_pio_writeb;
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ret->bus.pio_writew = qpci_pc_pio_writew;
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ret->bus.pio_writel = qpci_pc_pio_writel;
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ret->bus.mmio_readb = qpci_pc_mmio_readb;
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ret->bus.mmio_readw = qpci_pc_mmio_readw;
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ret->bus.mmio_readl = qpci_pc_mmio_readl;
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ret->bus.mmio_writeb = qpci_pc_mmio_writeb;
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ret->bus.mmio_writew = qpci_pc_mmio_writew;
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ret->bus.mmio_writel = qpci_pc_mmio_writel;
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ret->bus.config_readb = qpci_pc_config_readb;
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ret->bus.config_readw = qpci_pc_config_readw;
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@ -50,78 +50,76 @@ typedef struct QPCIBusSPAPR {
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* so PCI accessors need to swap data endianness
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*/
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static uint8_t qpci_spapr_io_readb(QPCIBus *bus, void *addr)
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static uint8_t qpci_spapr_pio_readb(QPCIBus *bus, uint32_t addr)
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{
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QPCIBusSPAPR *s = container_of(bus, QPCIBusSPAPR, bus);
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uint64_t port = (uintptr_t)addr;
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uint8_t v;
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if (port < s->pio.size) {
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v = readb(s->pio_cpu_base + port);
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} else {
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v = readb(s->mmio32_cpu_base + port);
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}
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return v;
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return readb(s->pio_cpu_base + addr);
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}
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static uint16_t qpci_spapr_io_readw(QPCIBus *bus, void *addr)
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static uint8_t qpci_spapr_mmio32_readb(QPCIBus *bus, uint32_t addr)
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{
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QPCIBusSPAPR *s = container_of(bus, QPCIBusSPAPR, bus);
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uint64_t port = (uintptr_t)addr;
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uint16_t v;
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if (port < s->pio.size) {
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v = readw(s->pio_cpu_base + port);
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} else {
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v = readw(s->mmio32_cpu_base + port);
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}
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return bswap16(v);
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return readb(s->mmio32_cpu_base + addr);
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}
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static uint32_t qpci_spapr_io_readl(QPCIBus *bus, void *addr)
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static void qpci_spapr_pio_writeb(QPCIBus *bus, uint32_t addr, uint8_t val)
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{
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QPCIBusSPAPR *s = container_of(bus, QPCIBusSPAPR, bus);
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uint64_t port = (uintptr_t)addr;
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uint32_t v;
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if (port < s->pio.size) {
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v = readl(s->pio_cpu_base + port);
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} else {
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v = readl(s->mmio32_cpu_base + port);
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}
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return bswap32(v);
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writeb(s->pio_cpu_base + addr, val);
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}
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static void qpci_spapr_io_writeb(QPCIBus *bus, void *addr, uint8_t value)
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static void qpci_spapr_mmio32_writeb(QPCIBus *bus, uint32_t addr, uint8_t val)
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{
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QPCIBusSPAPR *s = container_of(bus, QPCIBusSPAPR, bus);
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uint64_t port = (uintptr_t)addr;
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if (port < s->pio.size) {
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writeb(s->pio_cpu_base + port, value);
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} else {
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writeb(s->mmio32_cpu_base + port, value);
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}
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writeb(s->mmio32_cpu_base + addr, val);
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}
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static void qpci_spapr_io_writew(QPCIBus *bus, void *addr, uint16_t value)
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static uint16_t qpci_spapr_pio_readw(QPCIBus *bus, uint32_t addr)
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{
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QPCIBusSPAPR *s = container_of(bus, QPCIBusSPAPR, bus);
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uint64_t port = (uintptr_t)addr;
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value = bswap16(value);
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if (port < s->pio.size) {
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writew(s->pio_cpu_base + port, value);
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} else {
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writew(s->mmio32_cpu_base + port, value);
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}
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return bswap16(readw(s->pio_cpu_base + addr));
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}
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static void qpci_spapr_io_writel(QPCIBus *bus, void *addr, uint32_t value)
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static uint16_t qpci_spapr_mmio32_readw(QPCIBus *bus, uint32_t addr)
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{
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QPCIBusSPAPR *s = container_of(bus, QPCIBusSPAPR, bus);
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uint64_t port = (uintptr_t)addr;
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value = bswap32(value);
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if (port < s->pio.size) {
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writel(s->pio_cpu_base + port, value);
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} else {
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writel(s->mmio32_cpu_base + port, value);
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}
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return bswap16(readw(s->mmio32_cpu_base + addr));
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}
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static void qpci_spapr_pio_writew(QPCIBus *bus, uint32_t addr, uint16_t val)
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{
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QPCIBusSPAPR *s = container_of(bus, QPCIBusSPAPR, bus);
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writew(s->pio_cpu_base + addr, bswap16(val));
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}
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static void qpci_spapr_mmio32_writew(QPCIBus *bus, uint32_t addr, uint16_t val)
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{
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QPCIBusSPAPR *s = container_of(bus, QPCIBusSPAPR, bus);
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writew(s->mmio32_cpu_base + addr, bswap16(val));
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}
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static uint32_t qpci_spapr_pio_readl(QPCIBus *bus, uint32_t addr)
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{
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QPCIBusSPAPR *s = container_of(bus, QPCIBusSPAPR, bus);
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return bswap32(readl(s->pio_cpu_base + addr));
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}
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static uint32_t qpci_spapr_mmio32_readl(QPCIBus *bus, uint32_t addr)
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{
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QPCIBusSPAPR *s = container_of(bus, QPCIBusSPAPR, bus);
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return bswap32(readl(s->mmio32_cpu_base + addr));
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}
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static void qpci_spapr_pio_writel(QPCIBus *bus, uint32_t addr, uint32_t val)
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{
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QPCIBusSPAPR *s = container_of(bus, QPCIBusSPAPR, bus);
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writel(s->pio_cpu_base + addr, bswap32(val));
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}
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static void qpci_spapr_mmio32_writel(QPCIBus *bus, uint32_t addr, uint32_t val)
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{
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QPCIBusSPAPR *s = container_of(bus, QPCIBusSPAPR, bus);
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writel(s->mmio32_cpu_base + addr, bswap32(val));
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}
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static uint8_t qpci_spapr_config_readb(QPCIBus *bus, int devfn, uint8_t offset)
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@ -248,13 +246,21 @@ QPCIBus *qpci_init_spapr(QGuestAllocator *alloc)
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ret->alloc = alloc;
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ret->bus.io_readb = qpci_spapr_io_readb;
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ret->bus.io_readw = qpci_spapr_io_readw;
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ret->bus.io_readl = qpci_spapr_io_readl;
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ret->bus.pio_readb = qpci_spapr_pio_readb;
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ret->bus.pio_readw = qpci_spapr_pio_readw;
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ret->bus.pio_readl = qpci_spapr_pio_readl;
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ret->bus.io_writeb = qpci_spapr_io_writeb;
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ret->bus.io_writew = qpci_spapr_io_writew;
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ret->bus.io_writel = qpci_spapr_io_writel;
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ret->bus.pio_writeb = qpci_spapr_pio_writeb;
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ret->bus.pio_writew = qpci_spapr_pio_writew;
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ret->bus.pio_writel = qpci_spapr_pio_writel;
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ret->bus.mmio_readb = qpci_spapr_mmio32_readb;
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ret->bus.mmio_readw = qpci_spapr_mmio32_readw;
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ret->bus.mmio_readl = qpci_spapr_mmio32_readl;
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ret->bus.mmio_writeb = qpci_spapr_mmio32_writeb;
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ret->bus.mmio_writew = qpci_spapr_mmio32_writew;
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ret->bus.mmio_writel = qpci_spapr_mmio32_writel;
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ret->bus.config_readb = qpci_spapr_config_readb;
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ret->bus.config_readw = qpci_spapr_config_readw;
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@ -224,33 +224,68 @@ void qpci_config_writel(QPCIDevice *dev, uint8_t offset, uint32_t value)
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uint8_t qpci_io_readb(QPCIDevice *dev, void *data)
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{
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return dev->bus->io_readb(dev->bus, data);
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uintptr_t addr = (uintptr_t)data;
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if (addr < QPCI_PIO_LIMIT) {
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return dev->bus->pio_readb(dev->bus, addr);
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} else {
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return dev->bus->mmio_readb(dev->bus, addr);
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}
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}
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uint16_t qpci_io_readw(QPCIDevice *dev, void *data)
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{
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return dev->bus->io_readw(dev->bus, data);
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uintptr_t addr = (uintptr_t)data;
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if (addr < QPCI_PIO_LIMIT) {
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return dev->bus->pio_readw(dev->bus, addr);
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} else {
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return dev->bus->mmio_readw(dev->bus, addr);
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}
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}
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uint32_t qpci_io_readl(QPCIDevice *dev, void *data)
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{
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return dev->bus->io_readl(dev->bus, data);
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}
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uintptr_t addr = (uintptr_t)data;
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if (addr < QPCI_PIO_LIMIT) {
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return dev->bus->pio_readl(dev->bus, addr);
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} else {
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return dev->bus->mmio_readl(dev->bus, addr);
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}
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}
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void qpci_io_writeb(QPCIDevice *dev, void *data, uint8_t value)
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{
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dev->bus->io_writeb(dev->bus, data, value);
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uintptr_t addr = (uintptr_t)data;
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if (addr < QPCI_PIO_LIMIT) {
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dev->bus->pio_writeb(dev->bus, addr, value);
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} else {
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dev->bus->mmio_writeb(dev->bus, addr, value);
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}
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}
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void qpci_io_writew(QPCIDevice *dev, void *data, uint16_t value)
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{
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dev->bus->io_writew(dev->bus, data, value);
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uintptr_t addr = (uintptr_t)data;
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if (addr < QPCI_PIO_LIMIT) {
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dev->bus->pio_writew(dev->bus, addr, value);
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} else {
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dev->bus->mmio_writew(dev->bus, addr, value);
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}
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}
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void qpci_io_writel(QPCIDevice *dev, void *data, uint32_t value)
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{
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dev->bus->io_writel(dev->bus, data, value);
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uintptr_t addr = (uintptr_t)data;
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if (addr < QPCI_PIO_LIMIT) {
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dev->bus->pio_writel(dev->bus, addr, value);
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} else {
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dev->bus->mmio_writel(dev->bus, addr, value);
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}
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}
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void *qpci_iomap(QPCIDevice *dev, int barno, uint64_t *sizeptr)
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@ -15,6 +15,8 @@
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#include "libqtest.h"
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#define QPCI_PIO_LIMIT 0x10000
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#define QPCI_DEVFN(dev, fn) (((dev) << 3) | (fn))
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typedef struct QPCIDevice QPCIDevice;
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||||
|
|
@ -22,13 +24,21 @@ typedef struct QPCIBus QPCIBus;
|
|||
|
||||
struct QPCIBus
|
||||
{
|
||||
uint8_t (*io_readb)(QPCIBus *bus, void *addr);
|
||||
uint16_t (*io_readw)(QPCIBus *bus, void *addr);
|
||||
uint32_t (*io_readl)(QPCIBus *bus, void *addr);
|
||||
uint8_t (*pio_readb)(QPCIBus *bus, uint32_t addr);
|
||||
uint16_t (*pio_readw)(QPCIBus *bus, uint32_t addr);
|
||||
uint32_t (*pio_readl)(QPCIBus *bus, uint32_t addr);
|
||||
|
||||
void (*io_writeb)(QPCIBus *bus, void *addr, uint8_t value);
|
||||
void (*io_writew)(QPCIBus *bus, void *addr, uint16_t value);
|
||||
void (*io_writel)(QPCIBus *bus, void *addr, uint32_t value);
|
||||
uint8_t (*mmio_readb)(QPCIBus *bus, uint32_t addr);
|
||||
uint16_t (*mmio_readw)(QPCIBus *bus, uint32_t addr);
|
||||
uint32_t (*mmio_readl)(QPCIBus *bus, uint32_t addr);
|
||||
|
||||
void (*pio_writeb)(QPCIBus *bus, uint32_t addr, uint8_t value);
|
||||
void (*pio_writew)(QPCIBus *bus, uint32_t addr, uint16_t value);
|
||||
void (*pio_writel)(QPCIBus *bus, uint32_t addr, uint32_t value);
|
||||
|
||||
void (*mmio_writeb)(QPCIBus *bus, uint32_t addr, uint8_t value);
|
||||
void (*mmio_writew)(QPCIBus *bus, uint32_t addr, uint16_t value);
|
||||
void (*mmio_writel)(QPCIBus *bus, uint32_t addr, uint32_t value);
|
||||
|
||||
uint8_t (*config_readb)(QPCIBus *bus, int devfn, uint8_t offset);
|
||||
uint16_t (*config_readw)(QPCIBus *bus, int devfn, uint8_t offset);
|
||||
|
|
|
|||
Loading…
Reference in New Issue