mirror of https://gitee.com/openkylin/qemu.git
malta: Move PCI interrupt handling from gt64xxx_pci to piix4
Handling PCI interrupts in piix4 increases cohesion and reduces differences between piix4 and piix3. Signed-off-by: Bernhard Beschow <shentey@gmail.com> Reviewed-by: Philippe Mathieu-Daudé <f4bug@amsat.org> Message-Id: <20220217101924.15347-3-shentey@gmail.com> Signed-off-by: Philippe Mathieu-Daudé <f4bug@amsat.org>
This commit is contained in:
Bernhard Beschow
Philippe Mathieu-Daudé
parent
c291635867
commit
a7fc988051
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@ -45,6 +45,7 @@ struct PIIX4State {
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PCIDevice dev;
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qemu_irq cpu_intr;
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qemu_irq *isa;
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qemu_irq i8259[ISA_NUM_IRQS];
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RTCState rtc;
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/* Reset Control Register */
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@ -54,6 +55,27 @@ struct PIIX4State {
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OBJECT_DECLARE_SIMPLE_TYPE(PIIX4State, PIIX4_PCI_DEVICE)
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static void piix4_set_irq(void *opaque, int irq_num, int level)
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{
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int i, pic_irq, pic_level;
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qemu_irq *pic = opaque;
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PCIBus *bus = pci_get_bus(piix4_dev);
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/* now we change the pic irq level according to the piix irq mappings */
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/* XXX: optimize */
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pic_irq = piix4_dev->config[PIIX_PIRQCA + irq_num];
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if (pic_irq < 16) {
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/* The pic level is the logical OR of all the PCI irqs mapped to it. */
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pic_level = 0;
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for (i = 0; i < 4; i++) {
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if (pic_irq == piix4_dev->config[PIIX_PIRQCA + i]) {
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pic_level |= pci_bus_get_irq_level(bus, i);
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}
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}
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qemu_set_irq(pic[pic_irq], pic_level);
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}
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}
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static void piix4_isa_reset(DeviceState *dev)
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{
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PIIX4State *d = PIIX4_PCI_DEVICE(dev);
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@ -248,8 +270,34 @@ static void piix4_register_types(void)
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type_init(piix4_register_types)
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static int pci_slot_get_pirq(PCIDevice *pci_dev, int irq_num)
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{
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int slot;
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slot = PCI_SLOT(pci_dev->devfn);
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switch (slot) {
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/* PIIX4 USB */
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case 10:
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return 3;
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/* AMD 79C973 Ethernet */
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case 11:
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return 1;
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/* Crystal 4281 Sound */
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case 12:
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return 2;
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/* PCI slot 1 to 4 */
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case 18 ... 21:
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return ((slot - 18) + irq_num) & 0x03;
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/* Unknown device, don't do any translation */
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default:
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return irq_num;
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}
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}
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DeviceState *piix4_create(PCIBus *pci_bus, ISABus **isa_bus, I2CBus **smbus)
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{
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PIIX4State *s;
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PCIDevice *pci;
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DeviceState *dev;
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int devfn = PCI_DEVFN(10, 0);
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@ -257,6 +305,7 @@ DeviceState *piix4_create(PCIBus *pci_bus, ISABus **isa_bus, I2CBus **smbus)
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pci = pci_create_simple_multifunction(pci_bus, devfn, true,
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TYPE_PIIX4_PCI_DEVICE);
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dev = DEVICE(pci);
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s = PIIX4_PCI_DEVICE(pci);
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if (isa_bus) {
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*isa_bus = ISA_BUS(qdev_get_child_bus(dev, "isa.0"));
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}
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@ -271,5 +320,11 @@ DeviceState *piix4_create(PCIBus *pci_bus, ISABus **isa_bus, I2CBus **smbus)
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NULL, 0, NULL);
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}
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pci_bus_irqs(pci_bus, piix4_set_irq, pci_slot_get_pirq, s->i8259, 4);
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for (int i = 0; i < ISA_NUM_IRQS; i++) {
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s->i8259[i] = qdev_get_gpio_in_named(dev, "isa", i);
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}
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return dev;
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}
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@ -29,7 +29,6 @@
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#include "hw/mips/mips.h"
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#include "hw/pci/pci.h"
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#include "hw/pci/pci_host.h"
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#include "hw/southbridge/piix.h"
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#include "migration/vmstate.h"
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#include "hw/intc/i8259.h"
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#include "hw/irq.h"
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@ -981,53 +980,6 @@ static const MemoryRegionOps isd_mem_ops = {
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},
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};
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static int gt64120_pci_map_irq(PCIDevice *pci_dev, int irq_num)
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{
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int slot;
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slot = PCI_SLOT(pci_dev->devfn);
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switch (slot) {
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/* PIIX4 USB */
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case 10:
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return 3;
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/* AMD 79C973 Ethernet */
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case 11:
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return 1;
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/* Crystal 4281 Sound */
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case 12:
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return 2;
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/* PCI slot 1 to 4 */
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case 18 ... 21:
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return ((slot - 18) + irq_num) & 0x03;
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/* Unknown device, don't do any translation */
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default:
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return irq_num;
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}
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}
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static void gt64120_pci_set_irq(void *opaque, int irq_num, int level)
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{
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int i, pic_irq, pic_level;
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qemu_irq *pic = opaque;
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PCIBus *bus = pci_get_bus(piix4_dev);
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/* now we change the pic irq level according to the piix irq mappings */
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/* XXX: optimize */
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pic_irq = piix4_dev->config[PIIX_PIRQCA + irq_num];
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if (pic_irq < 16) {
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/* The pic level is the logical OR of all the PCI irqs mapped to it. */
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pic_level = 0;
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for (i = 0; i < 4; i++) {
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if (pic_irq == piix4_dev->config[PIIX_PIRQCA + i]) {
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pic_level |= pci_bus_get_irq_level(bus, i);
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}
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}
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qemu_set_irq(pic[pic_irq], pic_level);
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}
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}
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static void gt64120_reset(DeviceState *dev)
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{
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GT64120State *s = GT64120_PCI_HOST_BRIDGE(dev);
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@ -1204,7 +1156,7 @@ static void gt64120_realize(DeviceState *dev, Error **errp)
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"gt64120-isd", 0x1000);
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}
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PCIBus *gt64120_register(qemu_irq *pic)
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PCIBus *gt64120_register(void)
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{
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GT64120State *d;
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PCIHostState *phb;
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@ -1215,12 +1167,10 @@ PCIBus *gt64120_register(qemu_irq *pic)
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phb = PCI_HOST_BRIDGE(dev);
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memory_region_init(&d->pci0_mem, OBJECT(dev), "pci0-mem", 4 * GiB);
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address_space_init(&d->pci0_mem_as, &d->pci0_mem, "pci0-mem");
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phb->bus = pci_register_root_bus(dev, "pci",
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gt64120_pci_set_irq, gt64120_pci_map_irq,
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pic,
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&d->pci0_mem,
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get_system_io(),
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PCI_DEVFN(18, 0), 4, TYPE_PCI_BUS);
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phb->bus = pci_root_bus_new(dev, "pci",
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&d->pci0_mem,
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get_system_io(),
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PCI_DEVFN(18, 0), TYPE_PCI_BUS);
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sysbus_realize_and_unref(SYS_BUS_DEVICE(dev), &error_fatal);
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pci_create_simple(phb->bus, PCI_DEVFN(0, 0), "gt64120_pci");
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@ -97,7 +97,6 @@ struct MaltaState {
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Clock *cpuclk;
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MIPSCPSState cps;
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qemu_irq i8259[ISA_NUM_IRQS];
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};
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static struct _loaderparams {
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@ -1391,7 +1390,7 @@ void mips_malta_init(MachineState *machine)
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stl_p(memory_region_get_ram_ptr(bios_copy) + 0x10, 0x00000420);
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/* Northbridge */
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pci_bus = gt64120_register(s->i8259);
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pci_bus = gt64120_register();
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/*
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* The whole address space decoded by the GT-64120A doesn't generate
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* exception when accessing invalid memory. Create an empty slot to
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@ -1404,9 +1403,6 @@ void mips_malta_init(MachineState *machine)
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/* Interrupt controller */
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qdev_connect_gpio_out_named(dev, "intr", 0, i8259_irq);
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for (int i = 0; i < ISA_NUM_IRQS; i++) {
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s->i8259[i] = qdev_get_gpio_in_named(dev, "isa", i);
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}
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/* generate SPD EEPROM data */
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generate_eeprom_spd(&smbus_eeprom_buf[0 * 256], ram_size);
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@ -10,7 +10,7 @@
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#include "exec/memory.h"
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/* gt64xxx.c */
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PCIBus *gt64120_register(qemu_irq *pic);
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PCIBus *gt64120_register(void);
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/* bonito.c */
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PCIBus *bonito_init(qemu_irq *pic);
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