mirror of https://gitee.com/openkylin/qemu.git
qemu-sparc update
-----BEGIN PGP SIGNATURE----- Version: GnuPG v1.4.12 (GNU/Linux) iQEcBAABAgAGBQJUv9o/AAoJEFvCxW+uDzIfTwcH/2XSisJynfECMgclwnyp1fbd xs5ZFP7pV2+eyrtOExiRX+CTOoEdiNxjlwO/sq4yrTkbUzPLDC9QoQonFK4GjXSA cNGCbvBusHgAzwyoqfzPmlX0FOGwgfEDoanPWFCq01Cf4vYCEJFDGxMj4OjgSQ7L VFIobD3Wsz9gNLF2bhj7YIbC1OYWFYLJuEeC+RzJ9+LJ36lmvijOqkfCVX6on69u 3T7Qc+CgBPeJFmiXdHmDAKlmV4muQ2wddxqxSrPLbepJdiwoNap+fEz6pydMEoqX zMM9VrwbBTNAogWaVdab9gOtsBmY9x0ERV8cwyx2ZTZwP2SUIF1VIg6cZanHb6I= =b+DY -----END PGP SIGNATURE----- Merge remote-tracking branch 'remotes/mcayland/tags/qemu-sparc-signed' into staging qemu-sparc update # gpg: Signature made Wed 21 Jan 2015 16:56:31 GMT using RSA key ID AE0F321F # gpg: Good signature from "Mark Cave-Ayland <mark.cave-ayland@ilande.co.uk>" * remotes/mcayland/tags/qemu-sparc-signed: disas/sparc: Remove unused data sparc_opcode_archs[] target-sparc: Mark gen_load_trap_state_at_tl() as !CONFIG_USER_ONLY target-sparc: is_translating_asi() is TARGET_SPARC64 only target-sparc: address_mask(), asi_address_mask() are TARGET_SPARC64 only target-sparc: Remove unused gen_op_subi_cc and gen_op_addi_cc Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
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commit
a805ca5401
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@ -80,19 +80,6 @@ typedef struct sparc_opcode_arch
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short supported;
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} sparc_opcode_arch;
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static const struct sparc_opcode_arch sparc_opcode_archs[];
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/* Return the bitmask of supported architectures for ARCH. */
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#define SPARC_OPCODE_SUPPORTED(ARCH) (sparc_opcode_archs[ARCH].supported)
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/* Non-zero if ARCH1 conflicts with ARCH2.
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IE: ARCH1 as a supported bit set that ARCH2 doesn't, and vice versa. */
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#define SPARC_OPCODE_CONFLICT_P(ARCH1, ARCH2) \
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(((SPARC_OPCODE_SUPPORTED (ARCH1) & SPARC_OPCODE_SUPPORTED (ARCH2)) \
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!= SPARC_OPCODE_SUPPORTED (ARCH1)) \
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&& ((SPARC_OPCODE_SUPPORTED (ARCH1) & SPARC_OPCODE_SUPPORTED (ARCH2)) \
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!= SPARC_OPCODE_SUPPORTED (ARCH2)))
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/* Structure of an opcode table entry. */
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typedef struct sparc_opcode
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@ -301,25 +288,6 @@ static const char *sparc_decode_sparclet_cpreg (int);
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otherwise. */
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#define v9notv9a (MASK_V9)
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/* Table of opcode architectures.
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The order is defined in opcode/sparc.h. */
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static const struct sparc_opcode_arch sparc_opcode_archs[] =
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{
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{ "v6", MASK_V6 },
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{ "v7", MASK_V6 | MASK_V7 },
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{ "v8", MASK_V6 | MASK_V7 | MASK_V8 },
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{ "sparclet", MASK_V6 | MASK_V7 | MASK_V8 | MASK_SPARCLET },
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{ "sparclite", MASK_V6 | MASK_V7 | MASK_V8 | MASK_SPARCLITE },
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/* ??? Don't some v8 privileged insns conflict with v9? */
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{ "v9", MASK_V6 | MASK_V7 | MASK_V8 | MASK_V9 },
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/* v9 with ultrasparc additions */
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{ "v9a", MASK_V6 | MASK_V7 | MASK_V8 | MASK_V9 | MASK_V9A },
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/* v9 with cheetah additions */
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{ "v9b", MASK_V6 | MASK_V7 | MASK_V8 | MASK_V9 | MASK_V9A | MASK_V9B },
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{ NULL, 0 }
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};
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/* Branch condition field. */
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#define COND(x) (((x) & 0xf) << 25)
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@ -250,6 +250,7 @@ static void replace_tlb_1bit_lru(SparcTLBEntry *tlb,
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#endif
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#if defined(TARGET_SPARC64) || defined(CONFIG_USER_ONLY)
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static inline target_ulong address_mask(CPUSPARCState *env1, target_ulong addr)
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{
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#ifdef TARGET_SPARC64
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@ -259,12 +260,14 @@ static inline target_ulong address_mask(CPUSPARCState *env1, target_ulong addr)
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#endif
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return addr;
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}
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#endif
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#ifdef TARGET_SPARC64
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/* returns true if access using this ASI is to have address translated by MMU
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otherwise access is to raw physical address */
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/* TODO: check sparc32 bits */
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static inline int is_translating_asi(int asi)
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{
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#ifdef TARGET_SPARC64
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/* Ultrasparc IIi translating asi
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- note this list is defined by cpu implementation
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*/
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@ -281,10 +284,6 @@ static inline int is_translating_asi(int asi)
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default:
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return 0;
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}
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#else
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/* TODO: check sparc32 bits */
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return 0;
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#endif
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}
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static inline target_ulong asi_address_mask(CPUSPARCState *env,
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@ -296,6 +295,7 @@ static inline target_ulong asi_address_mask(CPUSPARCState *env,
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return addr;
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}
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}
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#endif
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void helper_check_align(CPUSPARCState *env, target_ulong addr, uint32_t align)
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{
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@ -363,14 +363,6 @@ static inline void gen_mov_reg_C(TCGv reg, TCGv_i32 src)
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tcg_gen_andi_tl(reg, reg, 0x1);
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}
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static inline void gen_op_addi_cc(TCGv dst, TCGv src1, target_long src2)
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{
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tcg_gen_mov_tl(cpu_cc_src, src1);
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tcg_gen_movi_tl(cpu_cc_src2, src2);
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tcg_gen_addi_tl(cpu_cc_dst, cpu_cc_src, src2);
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tcg_gen_mov_tl(dst, cpu_cc_dst);
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}
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static inline void gen_op_add_cc(TCGv dst, TCGv src1, TCGv src2)
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{
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tcg_gen_mov_tl(cpu_cc_src, src1);
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@ -502,22 +494,6 @@ static void gen_op_addx_int(DisasContext *dc, TCGv dst, TCGv src1,
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}
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}
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static inline void gen_op_subi_cc(TCGv dst, TCGv src1, target_long src2, DisasContext *dc)
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{
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tcg_gen_mov_tl(cpu_cc_src, src1);
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tcg_gen_movi_tl(cpu_cc_src2, src2);
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if (src2 == 0) {
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tcg_gen_mov_tl(cpu_cc_dst, src1);
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tcg_gen_movi_i32(cpu_cc_op, CC_OP_LOGIC);
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dc->cc_op = CC_OP_LOGIC;
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} else {
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tcg_gen_subi_tl(cpu_cc_dst, cpu_cc_src, src2);
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tcg_gen_movi_i32(cpu_cc_op, CC_OP_SUB);
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dc->cc_op = CC_OP_SUB;
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}
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tcg_gen_mov_tl(dst, cpu_cc_dst);
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}
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static inline void gen_op_sub_cc(TCGv dst, TCGv src1, TCGv src2)
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{
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tcg_gen_mov_tl(cpu_cc_src, src1);
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@ -2324,6 +2300,7 @@ static void gen_fmovq(DisasContext *dc, DisasCompare *cmp, int rd, int rs)
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gen_update_fprs_dirty(qd);
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}
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#ifndef CONFIG_USER_ONLY
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static inline void gen_load_trap_state_at_tl(TCGv_ptr r_tsptr, TCGv_ptr cpu_env)
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{
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TCGv_i32 r_tl = tcg_temp_new_i32();
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@ -2348,6 +2325,7 @@ static inline void gen_load_trap_state_at_tl(TCGv_ptr r_tsptr, TCGv_ptr cpu_env)
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tcg_temp_free_i32(r_tl);
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}
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#endif
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static void gen_edge(DisasContext *dc, TCGv dst, TCGv s1, TCGv s2,
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int width, bool cc, bool left)
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