mirror of https://gitee.com/openkylin/qemu.git
ETRAX: More DMA context level related fixes.
* When hitting EOL (end of list) at the data descriptor level, the DMA should mark the current context-descriptor as disabled and perform a context-store so software can see whats goin on. * Context loads update RW_SAVED_DATA_BUF, data loads dont. This fixes an issue with ethernet bootstrapping. * Reorder the logic for processing out channels to be more like the one for input channels. git-svn-id: svn://svn.savannah.nongnu.org/qemu/trunk@4723 c046a42c-6fe2-441c-8c8c-71466251a162
This commit is contained in:
edgar_igl
parent
77b73de676
commit
a8303d18e0
110
hw/etraxfs_dma.c
110
hw/etraxfs_dma.c
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@ -267,23 +267,33 @@ static void channel_load_d(struct fs_dma_ctrl *ctrl, int c)
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target_phys_addr_t addr = channel_reg(ctrl, c, RW_SAVED_DATA);
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/* Load and decode. FIXME: handle endianness. */
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D(printf("%s addr=%x\n", __func__, addr));
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D(printf("%s ch=%d addr=%x\n", __func__, c, addr));
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cpu_physical_memory_read (addr,
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(void *) &ctrl->channels[c].current_d,
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sizeof ctrl->channels[c].current_d);
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D(dump_d(c, &ctrl->channels[c].current_d));
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ctrl->channels[c].regs[RW_DATA] = addr;
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ctrl->channels[c].regs[RW_SAVED_DATA_BUF] =
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(uint32_t)ctrl->channels[c].current_d.buf;
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}
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static void channel_store_c(struct fs_dma_ctrl *ctrl, int c)
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{
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target_phys_addr_t addr = channel_reg(ctrl, c, RW_GROUP_DOWN);
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/* Encode and store. FIXME: handle endianness. */
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D(printf("%s ch=%d addr=%x\n", __func__, c, addr));
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D(dump_d(c, &ctrl->channels[c].current_d));
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cpu_physical_memory_write (addr,
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(void *) &ctrl->channels[c].current_c,
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sizeof ctrl->channels[c].current_c);
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}
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static void channel_store_d(struct fs_dma_ctrl *ctrl, int c)
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{
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target_phys_addr_t addr = channel_reg(ctrl, c, RW_SAVED_DATA);
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/* Load and decode. FIXME: handle endianness. */
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D(printf("%s addr=%x\n", __func__, addr));
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/* Encode and store. FIXME: handle endianness. */
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D(printf("%s ch=%d addr=%x\n", __func__, c, addr));
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cpu_physical_memory_write (addr,
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(void *) &ctrl->channels[c].current_d,
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sizeof ctrl->channels[c].current_d);
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@ -326,20 +336,23 @@ static void channel_continue(struct fs_dma_ctrl *ctrl, int c)
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/* If the current descriptor cleared the eol flag and we had already
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reached eol state, do the continue. */
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if (!ctrl->channels[c].current_d.eol && ctrl->channels[c].eol) {
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D(printf("continue %d ok %x\n", c,
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D(printf("continue %d ok %p\n", c,
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ctrl->channels[c].current_d.next));
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ctrl->channels[c].regs[RW_SAVED_DATA] =
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(uint32_t) ctrl->channels[c].current_d.next;
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channel_load_d(ctrl, c);
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channel_start(ctrl, c);
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}
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ctrl->channels[c].regs[RW_SAVED_DATA_BUF] =
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(uint32_t) ctrl->channels[c].current_d.buf;
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}
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static void channel_stream_cmd(struct fs_dma_ctrl *ctrl, int c, uint32_t v)
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{
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unsigned int cmd = v & ((1 << 10) - 1);
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D(printf("%s cmd=%x\n", __func__, cmd));
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D(printf("%s ch=%d cmd=%x pc=%x\n",
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__func__, c, cmd, ctrl->env->pc));
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if (cmd & regk_dma_load_d) {
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channel_load_d(ctrl, c);
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if (cmd & regk_dma_burst)
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@ -348,6 +361,7 @@ static void channel_stream_cmd(struct fs_dma_ctrl *ctrl, int c, uint32_t v)
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if (cmd & regk_dma_load_c) {
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channel_load_c(ctrl, c);
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channel_start(ctrl, c);
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}
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}
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@ -382,11 +396,30 @@ static void channel_out_run(struct fs_dma_ctrl *ctrl, int c)
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saved_data_buf = channel_reg(ctrl, c, RW_SAVED_DATA_BUF);
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D(printf("buf=%x after=%x saved_data_buf=%x\n",
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D(fprintf(logfile, "ch=%d buf=%x after=%x saved_data_buf=%x\n",
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c,
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(uint32_t)ctrl->channels[c].current_d.buf,
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(uint32_t)ctrl->channels[c].current_d.after,
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saved_data_buf));
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len = (uint32_t) ctrl->channels[c].current_d.after;
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len -= saved_data_buf;
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if (len > sizeof buf)
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len = sizeof buf;
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cpu_physical_memory_read (saved_data_buf, buf, len);
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D(printf("channel %d pushes %x %u bytes\n", c,
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saved_data_buf, len));
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if (ctrl->channels[c].client->client.push)
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ctrl->channels[c].client->client.push(
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ctrl->channels[c].client->client.opaque, buf, len);
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else
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printf("WARNING: DMA ch%d dataloss, no attached client.\n", c);
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saved_data_buf += len;
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if (saved_data_buf == (uint32_t)ctrl->channels[c].current_d.after) {
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/* Done. Step to next. */
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if (ctrl->channels[c].current_d.out_eop) {
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@ -403,36 +436,26 @@ static void channel_out_run(struct fs_dma_ctrl *ctrl, int c)
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if (ctrl->channels[c].current_d.eol) {
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D(printf("channel %d EOL\n", c));
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ctrl->channels[c].eol = 1;
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/* Mark the context as disabled. */
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ctrl->channels[c].current_c.dis = 1;
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channel_store_c(ctrl, c);
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channel_stop(ctrl, c);
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} else {
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ctrl->channels[c].regs[RW_SAVED_DATA] =
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(uint32_t) ctrl->channels[c].current_d.next;
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/* Load new descriptor. */
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channel_load_d(ctrl, c);
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saved_data_buf = (uint32_t)
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ctrl->channels[c].current_d.buf;
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}
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channel_store_d(ctrl, c);
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ctrl->channels[c].regs[RW_SAVED_DATA_BUF] = saved_data_buf;
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D(dump_d(c, &ctrl->channels[c].current_d));
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return;
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}
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len = (uint32_t) ctrl->channels[c].current_d.after;
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len -= saved_data_buf;
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if (len > sizeof buf)
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len = sizeof buf;
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cpu_physical_memory_read (saved_data_buf, buf, len);
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D(printf("channel %d pushes %x %u bytes\n", c,
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saved_data_buf, len));
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/* TODO: Push content. */
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if (ctrl->channels[c].client->client.push)
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ctrl->channels[c].client->client.push(
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ctrl->channels[c].client->client.opaque, buf, len);
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else
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printf("WARNING: DMA ch%d dataloss, no attached client.\n", c);
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ctrl->channels[c].regs[RW_SAVED_DATA_BUF] += len;
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ctrl->channels[c].regs[RW_SAVED_DATA_BUF] = saved_data_buf;
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}
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static int channel_in_process(struct fs_dma_ctrl *ctrl, int c,
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@ -483,14 +506,19 @@ static int channel_in_process(struct fs_dma_ctrl *ctrl, int c,
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if (ctrl->channels[c].current_d.eol) {
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D(printf("channel %d EOL\n", c));
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ctrl->channels[c].eol = 1;
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/* Mark the context as disabled. */
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ctrl->channels[c].current_c.dis = 1;
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channel_store_c(ctrl, c);
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channel_stop(ctrl, c);
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} else {
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ctrl->channels[c].regs[RW_SAVED_DATA] =
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(uint32_t) ctrl->channels[c].current_d.next;
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/* Load new descriptor. */
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channel_load_d(ctrl, c);
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saved_data_buf =
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ctrl->channels[c].regs[RW_SAVED_DATA_BUF];
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saved_data_buf = (uint32_t)
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ctrl->channels[c].current_d.buf;
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}
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}
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@ -523,21 +551,21 @@ dma_readl (void *opaque, target_phys_addr_t addr)
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/* Make addr relative to this instances base. */
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c = fs_channel(ctrl->base, addr);
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addr &= 0x1fff;
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addr &= 0x1fff;
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switch (addr)
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{
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{
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case RW_STAT:
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r = ctrl->channels[c].state & 7;
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r |= ctrl->channels[c].eol << 5;
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r |= ctrl->channels[c].stream_cmd_src << 8;
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break;
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default:
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default:
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r = ctrl->channels[c].regs[addr];
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D(printf ("%s c=%d addr=%x pc=%x\n",
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__func__, c, addr, env->pc));
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break;
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}
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__func__, c, addr, ctrl->env->pc));
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break;
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}
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return r;
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}
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@ -560,7 +588,7 @@ dma_writel (void *opaque, target_phys_addr_t addr, uint32_t value)
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c = fs_channel(ctrl->base, addr);
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addr &= 0x1fff;
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switch (addr)
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{
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{
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case RW_DATA:
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ctrl->channels[c].regs[addr] = value;
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break;
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@ -591,13 +619,15 @@ dma_writel (void *opaque, target_phys_addr_t addr, uint32_t value)
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case RW_STREAM_CMD:
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ctrl->channels[c].regs[addr] = value;
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D(printf("stream_cmd ch=%d pc=%x\n",
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c, ctrl->env->pc));
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channel_stream_cmd(ctrl, c, value);
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break;
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default:
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D(printf ("%s c=%d %x %x pc=%x\n",
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__func__, c, addr, value, env->pc));
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break;
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default:
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D(printf ("%s c=%d %x %x pc=%x\n",
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__func__, c, addr, value, ctrl->env->pc));
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break;
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}
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}
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