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target/arm: Tidy condition in disas_simd_two_reg_misc 

Path analysis shows that size == 3 && !is_q has been eliminated.

Fixes: Coverity CID1385853
Signed-off-by: Richard Henderson <richard.henderson@linaro.org>
Reviewed-by: Alex Bennée <alex.bennee@linaro.org>
Message-id: 20180501180455.11214-3-richard.henderson@linaro.org
Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
This commit is contained in:
Richard Henderson 2018-05-04 18:05:51 +01:00 committed by Peter Maydell
parent 8dae469705
commit a8766e3172
1 changed files with 5 additions and 1 deletions
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6
target/arm/translate-a64.c
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@ -11473,7 +11473,11 @@ static void disas_simd_two_reg_misc(DisasContext *s, uint32_t insn)
/* All 64-bit element operations can be shared with scalar 2misc */ /* All 64-bit element operations can be shared with scalar 2misc */
int pass; int pass;
for (pass = 0; pass < (is_q ? 2 : 1); pass++) { /* Coverity claims (size == 3 && !is_q) has been eliminated
* from all paths leading to here.
*/
tcg_debug_assert(is_q);
for (pass = 0; pass < 2; pass++) {
TCGv_i64 tcg_op = tcg_temp_new_i64(); TCGv_i64 tcg_op = tcg_temp_new_i64();
TCGv_i64 tcg_res = tcg_temp_new_i64(); TCGv_i64 tcg_res = tcg_temp_new_i64();