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ppc/xive: Provide silent escalation support
When the 's' bit is set the escalation is said to be 'silent' or 'silent/gather'. In such configuration, the notification sequence is skipped and only the escalation sequence is performed. This is used to configure all the EQs of a vCPU to escalate on a single EQ which will then target the hypervisor. Signed-off-by: Cédric Le Goater <clg@kaod.org> Message-Id: <20190718115420.19919-8-clg@kaod.org> Signed-off-by: David Gibson <david@gibson.dropbear.id.au>
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@ -1485,6 +1485,13 @@ static void xive_router_end_notify(XiveRouter *xrtr, uint8_t end_blk,
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xive_router_write_end(xrtr, end_blk, end_idx, &end, 1);
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xive_router_write_end(xrtr, end_blk, end_idx, &end, 1);
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}
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}
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/*
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* When the END is silent, we skip the notification part.
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*/
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if (xive_end_is_silent_escalation(&end)) {
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goto do_escalation;
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}
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/*
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/*
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* The W7 format depends on the F bit in W6. It defines the type
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* The W7 format depends on the F bit in W6. It defines the type
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* of the notification :
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* of the notification :
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@ -1564,6 +1571,7 @@ static void xive_router_end_notify(XiveRouter *xrtr, uint8_t end_blk,
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*/
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*/
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}
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}
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do_escalation:
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/*
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/*
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* If activated, escalate notification using the ESe PQ bits and
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* If activated, escalate notification using the ESe PQ bits and
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* the EAS in w4-5
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* the EAS in w4-5
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@ -212,6 +212,8 @@ typedef struct XiveEND {
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#define xive_end_is_escalate(end) (be32_to_cpu((end)->w0) & END_W0_ESCALATE_CTL)
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#define xive_end_is_escalate(end) (be32_to_cpu((end)->w0) & END_W0_ESCALATE_CTL)
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#define xive_end_is_uncond_escalation(end) \
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#define xive_end_is_uncond_escalation(end) \
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(be32_to_cpu((end)->w0) & END_W0_UNCOND_ESCALATE)
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(be32_to_cpu((end)->w0) & END_W0_UNCOND_ESCALATE)
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#define xive_end_is_silent_escalation(end) \
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(be32_to_cpu((end)->w0) & END_W0_SILENT_ESCALATE)
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static inline uint64_t xive_end_qaddr(XiveEND *end)
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static inline uint64_t xive_end_qaddr(XiveEND *end)
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{
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{
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