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target-ppc: fix SPE evsplat* instructions 

The shifts in the gen_evsplat* functions were expecting rA to be masked,
not extracted, and so used the wrong shift amounts to sign-extend or pad
with zeroes.

Signed-off-by: Nathan Froyd <froydnj@codesourcery.com>
Signed-off-by: Aurelien Jarno <aurelien@aurel32.net>
This commit is contained in:
Nathan Froyd 2010-02-23 12:21:31 -08:00 committed by Aurelien Jarno
parent e6bba2ef49
commit ae01847f9c
1 changed files with 2 additions and 2 deletions
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4
target-ppc/translate.c
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@ -7001,7 +7001,7 @@ static inline void gen_evmergelohi(DisasContext *ctx)
}
static inline void gen_evsplati(DisasContext *ctx)
{
uint64_t imm = ((int32_t)(rA(ctx->opcode) << 11)) >> 27;
uint64_t imm = ((int32_t)(rA(ctx->opcode) << 27)) >> 27;
#if defined(TARGET_PPC64)
tcg_gen_movi_tl(cpu_gpr[rD(ctx->opcode)], (imm << 32) | imm);
@ -7012,7 +7012,7 @@ static inline void gen_evsplati(DisasContext *ctx)
}
static inline void gen_evsplatfi(DisasContext *ctx)
{
uint64_t imm = rA(ctx->opcode) << 11;
uint64_t imm = rA(ctx->opcode) << 27;
#if defined(TARGET_PPC64)
tcg_gen_movi_tl(cpu_gpr[rD(ctx->opcode)], (imm << 32) | imm);