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target/microblaze: Split out EDR from env->sregs 

Finish eliminating the sregs array in favor of individual members.
Does not correct the width of EDR, yet.

Tested-by: Edgar E. Iglesias <edgar.iglesias@xilinx.com>
Reviewed-by: Edgar E. Iglesias <edgar.iglesias@xilinx.com>
Signed-off-by: Richard Henderson <richard.henderson@linaro.org>
This commit is contained in:
Richard Henderson 2020-08-19 22:05:29 -07:00
parent 6fbf78f24a
commit af20a93acb
4 changed files with 12 additions and 19 deletions
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9
linux-user/elfload.c
View File

@ -1038,9 +1038,12 @@ static void elf_core_copy_regs(target_elf_gregset_t *regs, const CPUMBState *env
(*regs)[pos++] = tswapreg(env->regs[i]);
}
for (i = 0; i < 6; i++) {
(*regs)[pos++] = tswapreg(env->sregs[i]);
}
(*regs)[pos++] = tswapreg(env->pc);
(*regs)[pos++] = tswapreg(env->msr);
(*regs)[pos++] = 0;
(*regs)[pos++] = tswapreg(env->ear);
(*regs)[pos++] = 0;
(*regs)[pos++] = tswapreg(env->esr);
}
#endif /* TARGET_MICROBLAZE */

2
target/microblaze/cpu.h
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@ -242,7 +242,7 @@ struct CPUMBState {
uint64_t esr;
uint64_t fsr;
uint64_t btr;
uint64_t sregs[14];
uint64_t edr;
float_status fp_status;
/* Stack protectors. Yes, it's a hw feature. */
uint32_t slr, shr;

4
target/microblaze/gdbstub.c
View File

@ -81,7 +81,7 @@ int mb_cpu_gdb_read_register(CPUState *cs, GByteArray *mem_buf, int n)
val = env->pvr.regs[n - GDB_PVR0];
break;
case GDB_EDR:
val = env->sregs[SR_EDR];
val = env->edr;
break;
case GDB_SLR:
val = env->slr;
@ -137,7 +137,7 @@ int mb_cpu_gdb_write_register(CPUState *cs, uint8_t *mem_buf, int n)
env->pvr.regs[n - GDB_PVR0] = tmp;
break;
case GDB_EDR:
env->sregs[SR_EDR] = tmp;
env->edr = tmp;
break;
case GDB_SLR:
env->slr = tmp;

16
target/microblaze/translate.c
View File

@ -103,12 +103,6 @@ static const char *regnames[] =
"r24", "r25", "r26", "r27", "r28", "r29", "r30", "r31",
};
static const char *special_regnames[] =
{
"rpc", "rmsr", "sr2", "rear", "sr4", "resr", "sr6", "rfsr",
"sr8", "sr9", "sr10", "rbtr", "sr12", "redr"
};
static inline void t_sync_flags(DisasContext *dc)
{
/* Synch the tb dependent flags between translator and runtime. */
@ -1828,7 +1822,7 @@ void mb_cpu_dump_state(CPUState *cs, FILE *f, int flags)
/* Registers that aren't modeled are reported as 0 */
qemu_fprintf(f, "redr=%" PRIx64 " rpid=0 rzpr=0 rtlbx=0 rtlbsx=0 "
"rtlblo=0 rtlbhi=0\n", env->sregs[SR_EDR]);
"rtlblo=0 rtlbhi=0\n", env->edr);
qemu_fprintf(f, "slr=%x shr=%x\n", env->slr, env->shr);
for (i = 0; i < 32; i++) {
qemu_fprintf(f, "r%2.2d=%8.8x ", i, env->regs[i]);
@ -1881,12 +1875,8 @@ void mb_tcg_init(void)
tcg_global_mem_new_i64(cpu_env, offsetof(CPUMBState, fsr), "rfsr");
cpu_SR[SR_BTR] =
tcg_global_mem_new_i64(cpu_env, offsetof(CPUMBState, btr), "rbtr");
for (i = SR_BTR + 1; i < ARRAY_SIZE(cpu_SR); i++) {
cpu_SR[i] = tcg_global_mem_new_i64(cpu_env,
offsetof(CPUMBState, sregs[i]),
special_regnames[i]);
}
cpu_SR[SR_EDR] =
tcg_global_mem_new_i64(cpu_env, offsetof(CPUMBState, edr), "redr");
}
void restore_state_to_opc(CPUMBState *env, TranslationBlock *tb,