mirror of https://gitee.com/openkylin/qemu.git
SPARC: Emulation of Leon3
Leon3 is an open-source VHDL System-On-Chip, well known in space industry (more information on http://www.gaisler.com). Leon3 is made of multiple components available in the GrLib VHDL library. Three devices are implemented: uart, timers and IRQ manager. You can find code for these peripherals in the grlib_* files. Signed-off-by: Fabien Chouteau <chouteau@adacore.com> Signed-off-by: Blue Swirl <blauwirbel@gmail.com>
This commit is contained in:
Fabien Chouteau
Blue Swirl
parent
8b1e132074
commit
b04d989054
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@ -286,7 +286,10 @@ obj-sparc-y += cirrus_vga.o
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else
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obj-sparc-y = sun4m.o lance.o tcx.o sun4m_iommu.o slavio_intctl.o
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obj-sparc-y += slavio_timer.o slavio_misc.o sparc32_dma.o
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obj-sparc-y += cs4231.o eccmemctl.o sbi.o sun4c_intctl.o
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obj-sparc-y += cs4231.o eccmemctl.o sbi.o sun4c_intctl.o leon3.o
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# GRLIB
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obj-sparc-y += grlib_gptimer.o grlib_irqmp.o grlib_apbuart.o
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endif
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obj-arm-y = integratorcp.o versatilepb.o arm_pic.o arm_timer.o
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@ -0,0 +1,218 @@
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/*
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* QEMU Leon3 System Emulator
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*
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* Copyright (c) 2010-2011 AdaCore
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*
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* Permission is hereby granted, free of charge, to any person obtaining a copy
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* of this software and associated documentation files (the "Software"), to deal
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* in the Software without restriction, including without limitation the rights
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* to use, copy, modify, merge, publish, distribute, sublicense, and/or sell
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* copies of the Software, and to permit persons to whom the Software is
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* furnished to do so, subject to the following conditions:
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*
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* The above copyright notice and this permission notice shall be included in
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* all copies or substantial portions of the Software.
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*
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* THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
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* IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
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* FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
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* THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
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* LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM,
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* OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN
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* THE SOFTWARE.
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*/
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#include "hw.h"
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#include "qemu-timer.h"
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#include "qemu-char.h"
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#include "sysemu.h"
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#include "boards.h"
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#include "loader.h"
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#include "elf.h"
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#include "trace.h"
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#include "grlib.h"
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/* Default system clock. */
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#define CPU_CLK (40 * 1000 * 1000)
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#define PROM_FILENAME "u-boot.bin"
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#define MAX_PILS 16
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typedef struct ResetData {
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CPUState *env;
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uint32_t entry; /* save kernel entry in case of reset */
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} ResetData;
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static void main_cpu_reset(void *opaque)
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{
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ResetData *s = (ResetData *)opaque;
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CPUState *env = s->env;
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cpu_reset(env);
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env->halted = 0;
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env->pc = s->entry;
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env->npc = s->entry + 4;
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}
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static void leon3_irq_ack(void *irq_manager, int intno)
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{
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grlib_irqmp_ack((DeviceState *)irq_manager, intno);
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leon3_cache_control_int();
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}
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static void leon3_set_pil_in(void *opaque, uint32_t pil_in)
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{
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CPUState *env = (CPUState *)opaque;
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assert(env != NULL);
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env->pil_in = pil_in;
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if (env->pil_in && (env->interrupt_index == 0 ||
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(env->interrupt_index & ~15) == TT_EXTINT)) {
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unsigned int i;
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for (i = 15; i > 0; i--) {
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if (env->pil_in & (1 << i)) {
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int old_interrupt = env->interrupt_index;
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env->interrupt_index = TT_EXTINT | i;
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if (old_interrupt != env->interrupt_index) {
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trace_leon3_set_irq(i);
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cpu_interrupt(env, CPU_INTERRUPT_HARD);
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}
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break;
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}
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}
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} else if (!env->pil_in && (env->interrupt_index & ~15) == TT_EXTINT) {
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trace_leon3_reset_irq(env->interrupt_index & 15);
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env->interrupt_index = 0;
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cpu_reset_interrupt(env, CPU_INTERRUPT_HARD);
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}
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}
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static void leon3_generic_hw_init(ram_addr_t ram_size,
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const char *boot_device,
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const char *kernel_filename,
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const char *kernel_cmdline,
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const char *initrd_filename,
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const char *cpu_model)
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{
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CPUState *env;
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ram_addr_t ram_offset, prom_offset;
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int ret;
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char *filename;
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qemu_irq *cpu_irqs = NULL;
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int bios_size;
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int prom_size;
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ResetData *reset_info;
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/* Init CPU */
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if (!cpu_model) {
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cpu_model = "LEON3";
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}
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env = cpu_init(cpu_model);
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if (!env) {
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fprintf(stderr, "qemu: Unable to find Sparc CPU definition\n");
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exit(1);
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}
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cpu_sparc_set_id(env, 0);
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/* Reset data */
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reset_info = qemu_mallocz(sizeof(ResetData));
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reset_info->env = env;
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qemu_register_reset(main_cpu_reset, reset_info);
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/* Allocate IRQ manager */
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grlib_irqmp_create(0x80000200, env, &cpu_irqs, MAX_PILS, &leon3_set_pil_in);
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env->qemu_irq_ack = leon3_irq_ack;
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/* Allocate RAM */
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if ((uint64_t)ram_size > (1UL << 30)) {
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fprintf(stderr,
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"qemu: Too much memory for this machine: %d, maximum 1G\n",
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(unsigned int)(ram_size / (1024 * 1024)));
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exit(1);
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}
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ram_offset = qemu_ram_alloc(NULL, "leon3.ram", ram_size);
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cpu_register_physical_memory(0x40000000, ram_size, ram_offset | IO_MEM_RAM);
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/* Allocate BIOS */
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prom_size = 8 * 1024 * 1024; /* 8Mb */
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prom_offset = qemu_ram_alloc(NULL, "Leon3.bios", prom_size);
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cpu_register_physical_memory(0x00000000, prom_size,
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prom_offset | IO_MEM_ROM);
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/* Load boot prom */
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if (bios_name == NULL) {
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bios_name = PROM_FILENAME;
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}
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filename = qemu_find_file(QEMU_FILE_TYPE_BIOS, bios_name);
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bios_size = get_image_size(filename);
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if (bios_size > prom_size) {
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fprintf(stderr, "qemu: could not load prom '%s': file too big\n",
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filename);
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exit(1);
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}
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if (bios_size > 0) {
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ret = load_image_targphys(filename, 0x00000000, bios_size);
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if (ret < 0 || ret > prom_size) {
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fprintf(stderr, "qemu: could not load prom '%s'\n", filename);
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exit(1);
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}
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} else if (kernel_filename == NULL) {
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fprintf(stderr, "Can't read bios image %s\n", filename);
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exit(1);
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}
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/* Can directly load an application. */
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if (kernel_filename != NULL) {
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long kernel_size;
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uint64_t entry;
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kernel_size = load_elf(kernel_filename, NULL, NULL, &entry, NULL, NULL,
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1 /* big endian */, ELF_MACHINE, 0);
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if (kernel_size < 0) {
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fprintf(stderr, "qemu: could not load kernel '%s'\n",
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kernel_filename);
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exit(1);
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}
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if (bios_size <= 0) {
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/* If there is no bios/monitor, start the application. */
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env->pc = entry;
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env->npc = entry + 4;
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reset_info->entry = entry;
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}
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}
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/* Allocate timers */
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grlib_gptimer_create(0x80000300, 2, CPU_CLK, cpu_irqs, 6);
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/* Allocate uart */
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if (serial_hds[0]) {
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grlib_apbuart_create(0x80000100, serial_hds[0], cpu_irqs[3]);
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}
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}
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QEMUMachine leon3_generic_machine = {
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.name = "leon3_generic",
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.desc = "Leon-3 generic",
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.init = leon3_generic_hw_init,
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.use_scsi = 0,
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};
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static void leon3_machine_init(void)
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{
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qemu_register_machine(&leon3_generic_machine);
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}
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machine_init(leon3_machine_init);
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@ -252,20 +252,21 @@ typedef struct sparc_def_t {
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uint32_t maxtl;
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} sparc_def_t;
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#define CPU_FEATURE_FLOAT (1 << 0)
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#define CPU_FEATURE_FLOAT128 (1 << 1)
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#define CPU_FEATURE_SWAP (1 << 2)
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#define CPU_FEATURE_MUL (1 << 3)
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#define CPU_FEATURE_DIV (1 << 4)
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#define CPU_FEATURE_FLUSH (1 << 5)
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#define CPU_FEATURE_FSQRT (1 << 6)
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#define CPU_FEATURE_FMUL (1 << 7)
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#define CPU_FEATURE_VIS1 (1 << 8)
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#define CPU_FEATURE_VIS2 (1 << 9)
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#define CPU_FEATURE_FSMULD (1 << 10)
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#define CPU_FEATURE_HYPV (1 << 11)
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#define CPU_FEATURE_CMT (1 << 12)
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#define CPU_FEATURE_GL (1 << 13)
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#define CPU_FEATURE_FLOAT (1 << 0)
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#define CPU_FEATURE_FLOAT128 (1 << 1)
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#define CPU_FEATURE_SWAP (1 << 2)
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#define CPU_FEATURE_MUL (1 << 3)
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#define CPU_FEATURE_DIV (1 << 4)
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#define CPU_FEATURE_FLUSH (1 << 5)
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#define CPU_FEATURE_FSQRT (1 << 6)
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#define CPU_FEATURE_FMUL (1 << 7)
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#define CPU_FEATURE_VIS1 (1 << 8)
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#define CPU_FEATURE_VIS2 (1 << 9)
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#define CPU_FEATURE_FSMULD (1 << 10)
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#define CPU_FEATURE_HYPV (1 << 11)
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#define CPU_FEATURE_CMT (1 << 12)
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#define CPU_FEATURE_GL (1 << 13)
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#define CPU_FEATURE_TA0_SHUTDOWN (1 << 14) /* Shutdown on "ta 0x0" */
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#ifndef TARGET_SPARC64
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#define CPU_DEFAULT_FEATURES (CPU_FEATURE_FLOAT | CPU_FEATURE_SWAP | \
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CPU_FEATURE_MUL | CPU_FEATURE_DIV | \
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@ -437,6 +438,12 @@ typedef struct CPUSPARCState {
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#define SOFTINT_REG_MASK (SOFTINT_STIMER|SOFTINT_INTRMASK|SOFTINT_TIMER)
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#endif
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sparc_def_t *def;
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void *irq_manager;
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void (*qemu_irq_ack) (void *irq_manager, int intno);
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/* Leon3 cache control */
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uint32_t cache_control;
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} CPUSPARCState;
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#ifndef NO_CPU_IO_DEFS
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@ -469,6 +476,8 @@ int cpu_cwp_inc(CPUState *env1, int cwp);
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int cpu_cwp_dec(CPUState *env1, int cwp);
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void cpu_set_cwp(CPUState *env1, int new_cwp);
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void leon3_cache_control_int(void);
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/* sun4m.c, sun4u.c */
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void cpu_check_irqs(CPUSPARCState *env);
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@ -770,6 +770,7 @@ void cpu_reset(CPUSPARCState *env)
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env->pc = 0;
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env->npc = env->pc + 4;
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#endif
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env->cache_control = 0;
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}
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static int cpu_sparc_register(CPUSPARCState *env, const char *cpu_model)
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@ -1274,20 +1275,20 @@ static const sparc_def_t sparc_defs[] = {
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.mmu_sfsr_mask = 0xffffffff,
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.mmu_trcr_mask = 0xffffffff,
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.nwindows = 8,
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.features = CPU_DEFAULT_FEATURES,
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.features = CPU_DEFAULT_FEATURES | CPU_FEATURE_TA0_SHUTDOWN,
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},
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{
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.name = "LEON3",
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.iu_version = 0xf3000000,
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.fpu_version = 4 << 17, /* FPU version 4 (Meiko) */
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.mmu_version = 0xf3000000,
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.mmu_bm = 0x00004000,
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.mmu_bm = 0x00000000,
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.mmu_ctpr_mask = 0x007ffff0,
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.mmu_cxr_mask = 0x0000003f,
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.mmu_sfsr_mask = 0xffffffff,
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.mmu_trcr_mask = 0xffffffff,
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.nwindows = 8,
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.features = CPU_DEFAULT_FEATURES,
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.features = CPU_DEFAULT_FEATURES | CPU_FEATURE_TA0_SHUTDOWN,
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},
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#endif
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};
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@ -85,6 +85,7 @@ DEF_HELPER_0(fcmpeq_fcc2, void)
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DEF_HELPER_0(fcmpeq_fcc3, void)
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#endif
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DEF_HELPER_1(raise_exception, void, int)
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DEF_HELPER_0(shutdown, void)
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#define F_HELPER_0_0(name) DEF_HELPER_0(f ## name, void)
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#define F_HELPER_DQ_0_0(name) \
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F_HELPER_0_0(name ## d); \
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@ -1,6 +1,7 @@
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#include "exec.h"
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#include "host-utils.h"
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#include "helper.h"
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#include "sysemu.h"
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//#define DEBUG_MMU
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//#define DEBUG_MXCC
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@ -9,6 +10,7 @@
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//#define DEBUG_ASI
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//#define DEBUG_PCALL
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//#define DEBUG_PSTATE
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//#define DEBUG_CACHE_CONTROL
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#ifdef DEBUG_MMU
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#define DPRINTF_MMU(fmt, ...) \
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@ -36,6 +38,13 @@
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#define DPRINTF_PSTATE(fmt, ...) do {} while (0)
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#endif
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#ifdef DEBUG_CACHE_CONTROL
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#define DPRINTF_CACHE_CONTROL(fmt, ...) \
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do { printf("CACHE_CONTROL: " fmt , ## __VA_ARGS__); } while (0)
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#else
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#define DPRINTF_CACHE_CONTROL(fmt, ...) do {} while (0)
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#endif
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#ifdef TARGET_SPARC64
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#ifndef TARGET_ABI32
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#define AM_CHECK(env1) ((env1)->pstate & PS_AM)
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@ -49,6 +58,27 @@
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#define QT0 (env->qt0)
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#define QT1 (env->qt1)
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/* Leon3 cache control */
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/* Cache control: emulate the behavior of cache control registers but without
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any effect on the emulated */
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#define CACHE_STATE_MASK 0x3
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#define CACHE_DISABLED 0x0
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#define CACHE_FROZEN 0x1
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#define CACHE_ENABLED 0x3
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/* Cache Control register fields */
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#define CACHE_CTRL_IF (1 << 4) /* Instruction Cache Freeze on Interrupt */
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#define CACHE_CTRL_DF (1 << 5) /* Data Cache Freeze on Interrupt */
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#define CACHE_CTRL_DP (1 << 14) /* Data cache flush pending */
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#define CACHE_CTRL_IP (1 << 15) /* Instruction cache flush pending */
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#define CACHE_CTRL_IB (1 << 16) /* Instruction burst fetch */
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#define CACHE_CTRL_FI (1 << 21) /* Flush Instruction cache (Write only) */
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#define CACHE_CTRL_FD (1 << 22) /* Flush Data cache (Write only) */
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#define CACHE_CTRL_DS (1 << 23) /* Data cache snoop enable */
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#if defined(CONFIG_USER_ONLY) && defined(TARGET_SPARC64)
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static void do_unassigned_access(target_ulong addr, int is_write, int is_exec,
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int is_asi, int size);
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@ -294,6 +324,13 @@ void HELPER(raise_exception)(int tt)
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raise_exception(tt);
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}
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void helper_shutdown(void)
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{
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#if !defined(CONFIG_USER_ONLY)
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qemu_system_shutdown_request();
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#endif
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}
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void helper_check_align(target_ulong addr, uint32_t align)
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{
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if (addr & align) {
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@ -1612,6 +1649,103 @@ static void dump_asi(const char *txt, target_ulong addr, int asi, int size,
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#ifndef TARGET_SPARC64
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#ifndef CONFIG_USER_ONLY
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/* Leon3 cache control */
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void leon3_cache_control_int(void)
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{
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uint32_t state = 0;
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if (env->cache_control & CACHE_CTRL_IF) {
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/* Instruction cache state */
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state = env->cache_control & CACHE_STATE_MASK;
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if (state == CACHE_ENABLED) {
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state = CACHE_FROZEN;
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DPRINTF_CACHE_CONTROL("Instruction cache: freeze\n");
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}
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env->cache_control &= ~CACHE_STATE_MASK;
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env->cache_control |= state;
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}
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if (env->cache_control & CACHE_CTRL_DF) {
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/* Data cache state */
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state = (env->cache_control >> 2) & CACHE_STATE_MASK;
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if (state == CACHE_ENABLED) {
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state = CACHE_FROZEN;
|
||||
DPRINTF_CACHE_CONTROL("Data cache: freeze\n");
|
||||
}
|
||||
|
||||
env->cache_control &= ~(CACHE_STATE_MASK << 2);
|
||||
env->cache_control |= (state << 2);
|
||||
}
|
||||
}
|
||||
|
||||
static void leon3_cache_control_st(target_ulong addr, uint64_t val, int size)
|
||||
{
|
||||
DPRINTF_CACHE_CONTROL("st addr:%08x, val:%" PRIx64 ", size:%d\n",
|
||||
addr, val, size);
|
||||
|
||||
if (size != 4) {
|
||||
DPRINTF_CACHE_CONTROL("32bits only\n");
|
||||
return;
|
||||
}
|
||||
|
||||
switch (addr) {
|
||||
case 0x00: /* Cache control */
|
||||
|
||||
/* These values must always be read as zeros */
|
||||
val &= ~CACHE_CTRL_FD;
|
||||
val &= ~CACHE_CTRL_FI;
|
||||
val &= ~CACHE_CTRL_IB;
|
||||
val &= ~CACHE_CTRL_IP;
|
||||
val &= ~CACHE_CTRL_DP;
|
||||
|
||||
env->cache_control = val;
|
||||
break;
|
||||
case 0x04: /* Instruction cache configuration */
|
||||
case 0x08: /* Data cache configuration */
|
||||
/* Read Only */
|
||||
break;
|
||||
default:
|
||||
DPRINTF_CACHE_CONTROL("write unknown register %08x\n", addr);
|
||||
break;
|
||||
};
|
||||
}
|
||||
|
||||
static uint64_t leon3_cache_control_ld(target_ulong addr, int size)
|
||||
{
|
||||
uint64_t ret = 0;
|
||||
|
||||
if (size != 4) {
|
||||
DPRINTF_CACHE_CONTROL("32bits only\n");
|
||||
return 0;
|
||||
}
|
||||
|
||||
switch (addr) {
|
||||
case 0x00: /* Cache control */
|
||||
ret = env->cache_control;
|
||||
break;
|
||||
|
||||
/* Configuration registers are read and only always keep those
|
||||
predefined values */
|
||||
|
||||
case 0x04: /* Instruction cache configuration */
|
||||
ret = 0x10220000;
|
||||
break;
|
||||
case 0x08: /* Data cache configuration */
|
||||
ret = 0x18220000;
|
||||
break;
|
||||
default:
|
||||
DPRINTF_CACHE_CONTROL("read unknown register %08x\n", addr);
|
||||
break;
|
||||
};
|
||||
DPRINTF_CACHE_CONTROL("st addr:%08x, ret:%" PRIx64 ", size:%d\n",
|
||||
addr, ret, size);
|
||||
return ret;
|
||||
}
|
||||
|
||||
uint64_t helper_ld_asi(target_ulong addr, int asi, int size, int sign)
|
||||
{
|
||||
uint64_t ret = 0;
|
||||
|
|
@ -1621,8 +1755,13 @@ uint64_t helper_ld_asi(target_ulong addr, int asi, int size, int sign)
|
|||
|
||||
helper_check_align(addr, size - 1);
|
||||
switch (asi) {
|
||||
case 2: /* SuperSparc MXCC registers */
|
||||
case 2: /* SuperSparc MXCC registers and Leon3 cache control */
|
||||
switch (addr) {
|
||||
case 0x00: /* Leon3 Cache Control */
|
||||
case 0x08: /* Leon3 Instruction Cache config */
|
||||
case 0x0C: /* Leon3 Date Cache config */
|
||||
ret = leon3_cache_control_ld(addr, size);
|
||||
break;
|
||||
case 0x01c00a00: /* MXCC control register */
|
||||
if (size == 8)
|
||||
ret = env->mxccregs[3];
|
||||
|
|
@ -1850,8 +1989,14 @@ void helper_st_asi(target_ulong addr, uint64_t val, int asi, int size)
|
|||
{
|
||||
helper_check_align(addr, size - 1);
|
||||
switch(asi) {
|
||||
case 2: /* SuperSparc MXCC registers */
|
||||
case 2: /* SuperSparc MXCC registers and Leon3 cache control */
|
||||
switch (addr) {
|
||||
case 0x00: /* Leon3 Cache Control */
|
||||
case 0x08: /* Leon3 Instruction Cache config */
|
||||
case 0x0C: /* Leon3 Date Cache config */
|
||||
leon3_cache_control_st(addr, val, size);
|
||||
break;
|
||||
|
||||
case 0x01c00000: /* MXCC stream data register 0 */
|
||||
if (size == 8)
|
||||
env->mxccdata[0] = val;
|
||||
|
|
@ -4177,6 +4322,13 @@ void do_interrupt(CPUState *env)
|
|||
env->pc = env->tbr;
|
||||
env->npc = env->pc + 4;
|
||||
env->exception_index = -1;
|
||||
|
||||
#if !defined(CONFIG_USER_ONLY)
|
||||
/* IRQ acknowledgment */
|
||||
if ((intno & ~15) == TT_EXTINT && env->qemu_irq_ack != NULL) {
|
||||
env->qemu_irq_ack(env->irq_manager, intno);
|
||||
}
|
||||
#endif
|
||||
}
|
||||
#endif
|
||||
|
||||
|
|
|
|||
|
|
@ -1997,8 +1997,9 @@ static void disas_sparc_insn(DisasContext * dc)
|
|||
} else
|
||||
tcg_gen_mov_tl(cpu_dst, cpu_src1);
|
||||
}
|
||||
|
||||
cond = GET_FIELD(insn, 3, 6);
|
||||
if (cond == 0x8) {
|
||||
if (cond == 0x8) { /* Trap Always */
|
||||
save_state(dc, cpu_cond);
|
||||
if ((dc->def->features & CPU_FEATURE_HYPV) &&
|
||||
supervisor(dc))
|
||||
|
|
@ -2007,7 +2008,15 @@ static void disas_sparc_insn(DisasContext * dc)
|
|||
tcg_gen_andi_tl(cpu_dst, cpu_dst, V8_TRAP_MASK);
|
||||
tcg_gen_addi_tl(cpu_dst, cpu_dst, TT_TRAP);
|
||||
tcg_gen_trunc_tl_i32(cpu_tmp32, cpu_dst);
|
||||
gen_helper_raise_exception(cpu_tmp32);
|
||||
|
||||
if (rs2 == 0 &&
|
||||
dc->def->features & CPU_FEATURE_TA0_SHUTDOWN) {
|
||||
|
||||
gen_helper_shutdown();
|
||||
|
||||
} else {
|
||||
gen_helper_raise_exception(cpu_tmp32);
|
||||
}
|
||||
} else if (cond != 0) {
|
||||
TCGv r_cond = tcg_temp_new();
|
||||
int l1;
|
||||
|
|
|
|||
|
|
@ -244,3 +244,7 @@ disable grlib_irqmp_unknown_register(const char *op, uint64_t val) "%s unknown r
|
|||
# hw/grlib_apbuart.c
|
||||
disable grlib_apbuart_event(int event) "event:%d"
|
||||
disable grlib_apbuart_unknown_register(const char *op, uint64_t val) "%s unknown register 0x%"PRIx64""
|
||||
|
||||
# hw/leon3.c
|
||||
disable leon3_set_irq(int intno) "Set CPU IRQ %d"
|
||||
disable leon3_reset_irq(int intno) "Reset CPU IRQ %d"
|
||||
|
|
|
|||
Loading…
Reference in New Issue