mirror of https://gitee.com/openkylin/qemu.git
target/mips: Update gen_flt_ldst()
Update gen_flt_ldst() in order to reuse the functions for nanoMIPS Signed-off-by: Yongbok Kim <yongbok.kim@mips.com> Reviewed-by: Philippe Mathieu-Daudé <f4bug@amsat.org> Reviewed-by: Aleksandar Markovic <aleksandar.markovic@mips.com> Signed-off-by: Aleksandar Markovic <aleksandar.markovic@mips.com>
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@ -2433,11 +2433,8 @@ static void gen_st_cond (DisasContext *ctx, uint32_t opc, int rt,
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/* Load and store */
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static void gen_flt_ldst (DisasContext *ctx, uint32_t opc, int ft,
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int base, int16_t offset)
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TCGv t0)
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{
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TCGv t0 = tcg_temp_new();
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gen_base_offset_addr(ctx, t0, base, offset);
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/* Don't do NOP if destination is zero: we must perform the actual
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memory access. */
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switch (opc) {
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@ -2480,15 +2477,15 @@ static void gen_flt_ldst (DisasContext *ctx, uint32_t opc, int ft,
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default:
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MIPS_INVAL("flt_ldst");
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generate_exception_end(ctx, EXCP_RI);
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goto out;
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break;
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}
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out:
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tcg_temp_free(t0);
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}
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static void gen_cop1_ldst(DisasContext *ctx, uint32_t op, int rt,
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int rs, int16_t imm)
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{
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TCGv t0 = tcg_temp_new();
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if (ctx->CP0_Config1 & (1 << CP0C1_FP)) {
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check_cp1_enabled(ctx);
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switch (op) {
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@ -2497,11 +2494,13 @@ static void gen_cop1_ldst(DisasContext *ctx, uint32_t op, int rt,
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check_insn(ctx, ISA_MIPS2);
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/* Fallthrough */
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default:
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gen_flt_ldst(ctx, op, rt, rs, imm);
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gen_base_offset_addr(ctx, t0, rs, imm);
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gen_flt_ldst(ctx, op, rt, t0);
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}
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} else {
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generate_exception_err(ctx, EXCP_CpU, 1);
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}
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tcg_temp_free(t0);
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}
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/* Arithmetic with immediate operand */
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