mirror of https://gitee.com/openkylin/qemu.git
Sparc: fix coding style in helper.c
Before the next patch, fix coding style of the areas affected. Reviewed-by: Richard Henderson <rth@twiddle.net> Signed-off-by: Blue Swirl <blauwirbel@gmail.com>
This commit is contained in:
Blue Swirl
parent
7a5e4488cd
commit
b7da25f003
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@ -25,7 +25,7 @@
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//#define DEBUG_MMU
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#ifdef DEBUG_MMU
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#define DPRINTF_MMU(fmt, ...) \
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#define DPRINTF_MMU(fmt, ...) \
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do { printf("MMU: " fmt , ## __VA_ARGS__); } while (0)
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#else
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#define DPRINTF_MMU(fmt, ...) do {} while (0)
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@ -38,10 +38,11 @@
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int cpu_sparc_handle_mmu_fault(CPUState *env1, target_ulong address, int rw,
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int mmu_idx)
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{
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if (rw & 2)
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if (rw & 2) {
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env1->exception_index = TT_TFAULT;
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else
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} else {
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env1->exception_index = TT_DFAULT;
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}
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return 1;
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}
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@ -100,7 +101,7 @@ static int get_physical_address(CPUState *env, target_phys_addr_t *physical,
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if ((env->mmuregs[0] & MMU_E) == 0) { /* MMU disabled */
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*page_size = TARGET_PAGE_SIZE;
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// Boot mode: instruction fetches are taken from PROM
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/* Boot mode: instruction fetches are taken from PROM */
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if (rw == 2 && (env->mmuregs[0] & env->def->mmu_bm)) {
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*physical = env->prom_addr | (address & 0x7ffffULL);
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*prot = PAGE_READ | PAGE_EXEC;
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@ -111,7 +112,7 @@ static int get_physical_address(CPUState *env, target_phys_addr_t *physical,
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return 0;
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}
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*access_index = ((rw & 1) << 2) | (rw & 2) | (is_user? 0 : 1);
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*access_index = ((rw & 1) << 2) | (rw & 2) | (is_user ? 0 : 1);
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*physical = 0xffffffffffff0000ULL;
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/* SPARC reference MMU table walk: Context table->L1->L2->PTE */
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@ -178,15 +179,17 @@ static int get_physical_address(CPUState *env, target_phys_addr_t *physical,
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/* check access */
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access_perms = (pde & PTE_ACCESS_MASK) >> PTE_ACCESS_SHIFT;
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error_code = access_table[*access_index][access_perms];
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if (error_code && !((env->mmuregs[0] & MMU_NF) && is_user))
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if (error_code && !((env->mmuregs[0] & MMU_NF) && is_user)) {
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return error_code;
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}
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/* update page modified and dirty bits */
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is_dirty = (rw & 1) && !(pde & PG_MODIFIED_MASK);
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if (!(pde & PG_ACCESSED_MASK) || is_dirty) {
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pde |= PG_ACCESSED_MASK;
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if (is_dirty)
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if (is_dirty) {
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pde |= PG_MODIFIED_MASK;
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}
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stl_phys_notdirty(pde_ptr, pde);
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}
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@ -205,8 +208,8 @@ static int get_physical_address(CPUState *env, target_phys_addr_t *physical,
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}
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/* Perform address translation */
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int cpu_sparc_handle_mmu_fault (CPUState *env, target_ulong address, int rw,
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int mmu_idx)
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int cpu_sparc_handle_mmu_fault(CPUState *env, target_ulong address, int rw,
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int mmu_idx)
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{
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target_phys_addr_t paddr;
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target_ulong vaddr;
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@ -226,25 +229,27 @@ int cpu_sparc_handle_mmu_fault (CPUState *env, target_ulong address, int rw,
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return 0;
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}
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if (env->mmuregs[3]) /* Fault status register */
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if (env->mmuregs[3]) { /* Fault status register */
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env->mmuregs[3] = 1; /* overflow (not read before another fault) */
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}
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env->mmuregs[3] |= (access_index << 5) | error_code | 2;
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env->mmuregs[4] = address; /* Fault address register */
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if ((env->mmuregs[0] & MMU_NF) || env->psret == 0) {
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// No fault mode: if a mapping is available, just override
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// permissions. If no mapping is available, redirect accesses to
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// neverland. Fake/overridden mappings will be flushed when
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// switching to normal mode.
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/* No fault mode: if a mapping is available, just override
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permissions. If no mapping is available, redirect accesses to
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neverland. Fake/overridden mappings will be flushed when
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switching to normal mode. */
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vaddr = address & TARGET_PAGE_MASK;
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prot = PAGE_READ | PAGE_WRITE | PAGE_EXEC;
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tlb_set_page(env, vaddr, paddr, prot, mmu_idx, TARGET_PAGE_SIZE);
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return 0;
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} else {
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if (rw & 2)
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if (rw & 2) {
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env->exception_index = TT_TFAULT;
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else
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} else {
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env->exception_index = TT_DFAULT;
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}
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return 1;
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}
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}
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@ -266,8 +271,9 @@ target_ulong mmu_probe(CPUState *env, target_ulong address, int mmulev)
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case 3: /* Reserved */
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return 0;
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case 1: /* L1 PDE */
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if (mmulev == 3)
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if (mmulev == 3) {
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return pde;
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}
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pde_ptr = ((address >> 22) & ~3) + ((pde & ~3) << 4);
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pde = ldl_phys(pde_ptr);
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@ -279,8 +285,9 @@ target_ulong mmu_probe(CPUState *env, target_ulong address, int mmulev)
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case 2: /* L1 PTE */
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return pde;
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case 1: /* L2 PDE */
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if (mmulev == 2)
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if (mmulev == 2) {
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return pde;
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}
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pde_ptr = ((address & 0xfc0000) >> 16) + ((pde & ~3) << 4);
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pde = ldl_phys(pde_ptr);
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@ -292,8 +299,9 @@ target_ulong mmu_probe(CPUState *env, target_ulong address, int mmulev)
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case 2: /* L2 PTE */
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return pde;
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case 1: /* L3 PDE */
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if (mmulev == 1)
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if (mmulev == 1) {
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return pde;
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}
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pde_ptr = ((address & 0x3f000) >> 10) + ((pde & ~3) << 4);
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pde = ldl_phys(pde_ptr);
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@ -434,7 +442,7 @@ int target_memory_rw_debug(CPUState *env, target_ulong addr,
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#else /* !TARGET_SPARC64 */
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// 41 bit physical address space
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/* 41 bit physical address space */
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static inline target_phys_addr_t ultrasparc_truncate_physical(uint64_t x)
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{
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return x & 0x1ffffffffffULL;
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@ -444,8 +452,9 @@ static inline target_phys_addr_t ultrasparc_truncate_physical(uint64_t x)
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* UltraSparc IIi I/DMMUs
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*/
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// Returns true if TTE tag is valid and matches virtual address value in context
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// requires virtual address mask value calculated from TTE entry size
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/* Returns true if TTE tag is valid and matches virtual address value
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in context requires virtual address mask value calculated from TTE
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entry size */
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static inline int ultrasparc_tag_match(SparcTLBEntry *tlb,
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uint64_t address, uint64_t context,
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target_phys_addr_t *physical)
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@ -454,26 +463,25 @@ static inline int ultrasparc_tag_match(SparcTLBEntry *tlb,
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switch (TTE_PGSIZE(tlb->tte)) {
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default:
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case 0x0: // 8k
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case 0x0: /* 8k */
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mask = 0xffffffffffffe000ULL;
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break;
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case 0x1: // 64k
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case 0x1: /* 64k */
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mask = 0xffffffffffff0000ULL;
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break;
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case 0x2: // 512k
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case 0x2: /* 512k */
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mask = 0xfffffffffff80000ULL;
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break;
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case 0x3: // 4M
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case 0x3: /* 4M */
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mask = 0xffffffffffc00000ULL;
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break;
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}
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// valid, context match, virtual address match?
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/* valid, context match, virtual address match? */
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if (TTE_IS_VALID(tlb->tte) &&
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(TTE_IS_GLOBAL(tlb->tte) || tlb_compare_context(tlb, context))
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&& compare_masked(address, tlb->tag, mask))
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{
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// decode physical address
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&& compare_masked(address, tlb->tag, mask)) {
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/* decode physical address */
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*physical = ((tlb->tte & mask) | (address & ~mask)) & 0x1ffffffe000ULL;
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return 1;
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}
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@ -498,7 +506,7 @@ static int get_physical_address_data(CPUState *env,
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return 0;
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}
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switch(mmu_idx) {
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switch (mmu_idx) {
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case MMU_USER_IDX:
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case MMU_KERNEL_IDX:
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context = env->dmmu.mmu_primary_context & 0x1fff;
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@ -524,11 +532,11 @@ static int get_physical_address_data(CPUState *env,
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}
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for (i = 0; i < 64; i++) {
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// ctx match, vaddr match, valid?
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/* ctx match, vaddr match, valid? */
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if (ultrasparc_tag_match(&env->dtlb[i], address, context, physical)) {
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int do_fault = 0;
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// access ok?
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/* access ok? */
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/* multiple bits in SFSR.FT may be set on TT_DFAULT */
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if (TTE_IS_PRIV(env->dtlb[i].tte) && is_user) {
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do_fault = 1;
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@ -632,10 +640,10 @@ static int get_physical_address_code(CPUState *env,
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}
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for (i = 0; i < 64; i++) {
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// ctx match, vaddr match, valid?
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/* ctx match, vaddr match, valid? */
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if (ultrasparc_tag_match(&env->itlb[i],
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address, context, physical)) {
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// access ok?
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/* access ok? */
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if (TTE_IS_PRIV(env->itlb[i].tte) && is_user) {
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/* Fault status register */
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if (env->immu.sfsr & SFSR_VALID_BIT) {
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@ -686,7 +694,7 @@ static int get_physical_address(CPUState *env, target_phys_addr_t *physical,
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everything when an entry is evicted. */
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*page_size = TARGET_PAGE_SIZE;
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#if defined (DEBUG_MMU)
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#if defined(DEBUG_MMU)
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/* safety net to catch wrong softmmu index use from dynamic code */
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if (env->tl > 0 && mmu_idx != MMU_NUCLEUS_IDX) {
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DPRINTF_MMU("get_physical_address %s tl=%d mmu_idx=%d"
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@ -702,17 +710,18 @@ static int get_physical_address(CPUState *env, target_phys_addr_t *physical,
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}
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#endif
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if (rw == 2)
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if (rw == 2) {
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return get_physical_address_code(env, physical, prot, address,
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mmu_idx);
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else
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} else {
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return get_physical_address_data(env, physical, prot, address, rw,
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mmu_idx);
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}
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}
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/* Perform address translation */
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int cpu_sparc_handle_mmu_fault (CPUState *env, target_ulong address, int rw,
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int mmu_idx)
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int cpu_sparc_handle_mmu_fault(CPUState *env, target_ulong address, int rw,
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int mmu_idx)
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{
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target_ulong virt_addr, vaddr;
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target_phys_addr_t paddr;
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@ -740,7 +749,7 @@ int cpu_sparc_handle_mmu_fault (CPUState *env, target_ulong address, int rw,
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tlb_set_page(env, vaddr, paddr, prot, mmu_idx, page_size);
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return 0;
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}
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// XXX
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/* XXX */
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return 1;
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}
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@ -785,7 +794,7 @@ void dump_mmu(FILE *f, fprintf_function cpu_fprintf, CPUState *env)
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TTE_IS_LOCKED(env->dtlb[i].tte) ?
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"locked" : "unlocked",
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env->dtlb[i].tag & (uint64_t)0x1fffULL,
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TTE_IS_GLOBAL(env->dtlb[i].tte)?
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TTE_IS_GLOBAL(env->dtlb[i].tte) ?
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"global" : "local");
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}
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}
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@ -821,7 +830,7 @@ void dump_mmu(FILE *f, fprintf_function cpu_fprintf, CPUState *env)
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TTE_IS_LOCKED(env->itlb[i].tte) ?
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"locked" : "unlocked",
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env->itlb[i].tag & (uint64_t)0x1fffULL,
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TTE_IS_GLOBAL(env->itlb[i].tte)?
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TTE_IS_GLOBAL(env->itlb[i].tte) ?
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"global" : "local");
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}
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}
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