mirror of https://gitee.com/openkylin/qemu.git
hpet: Drop static state
Instead of keeping a static reference around, pass the state to hpet_enabled and hpet_get_ticks. All callers now have it at hand. Will once allow to instantiate the HPET more than a single time. Signed-off-by: Jan Kiszka <jan.kiszka@siemens.com> Signed-off-by: Blue Swirl <blauwirbel@gmail.com>
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7d932dfdc5
commit
b7eaa6c77c
38
hw/hpet.c
38
hw/hpet.c
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@ -69,8 +69,6 @@ typedef struct HPETState {
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uint64_t hpet_counter; /* main counter */
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} HPETState;
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static HPETState *hpet_statep;
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static uint32_t hpet_in_legacy_mode(HPETState *s)
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{
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return s->config & HPET_CFG_LEGACY;
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@ -81,9 +79,9 @@ static uint32_t timer_int_route(struct HPETTimer *timer)
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return (timer->config & HPET_TN_INT_ROUTE_MASK) >> HPET_TN_INT_ROUTE_SHIFT;
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}
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static uint32_t hpet_enabled(void)
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static uint32_t hpet_enabled(HPETState *s)
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{
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return hpet_statep->config & HPET_CFG_ENABLE;
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return s->config & HPET_CFG_ENABLE;
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}
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static uint32_t timer_is_periodic(HPETTimer *t)
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@ -133,9 +131,9 @@ static int deactivating_bit(uint64_t old, uint64_t new, uint64_t mask)
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return ((old & mask) && !(new & mask));
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}
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static uint64_t hpet_get_ticks(void)
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static uint64_t hpet_get_ticks(HPETState *s)
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{
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return ns_to_ticks(qemu_get_clock(vm_clock) + hpet_statep->hpet_offset);
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return ns_to_ticks(qemu_get_clock(vm_clock) + s->hpet_offset);
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}
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/*
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@ -174,7 +172,7 @@ static void update_irq(struct HPETTimer *timer)
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} else {
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route = timer_int_route(timer);
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}
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if (!timer_enabled(timer) || !hpet_enabled()) {
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if (!timer_enabled(timer) || !hpet_enabled(timer->state)) {
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return;
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}
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qemu_irq_pulse(timer->state->irqs[route]);
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@ -185,7 +183,7 @@ static void hpet_pre_save(void *opaque)
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HPETState *s = opaque;
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/* save current counter value */
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s->hpet_counter = hpet_get_ticks();
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s->hpet_counter = hpet_get_ticks(s);
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}
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static int hpet_post_load(void *opaque, int version_id)
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@ -240,7 +238,7 @@ static void hpet_timer(void *opaque)
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uint64_t diff;
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uint64_t period = t->period;
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uint64_t cur_tick = hpet_get_ticks();
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uint64_t cur_tick = hpet_get_ticks(t->state);
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if (timer_is_periodic(t) && period != 0) {
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if (t->config & HPET_TN_32BIT) {
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@ -270,7 +268,7 @@ static void hpet_set_timer(HPETTimer *t)
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{
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uint64_t diff;
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uint32_t wrap_diff; /* how many ticks until we wrap? */
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uint64_t cur_tick = hpet_get_ticks();
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uint64_t cur_tick = hpet_get_ticks(t->state);
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/* whenever new timer is being set up, make sure wrap_flag is 0 */
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t->wrap_flag = 0;
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@ -353,16 +351,16 @@ static uint32_t hpet_ram_readl(void *opaque, target_phys_addr_t addr)
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DPRINTF("qemu: invalid HPET_CFG + 4 hpet_ram_readl \n");
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return 0;
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case HPET_COUNTER:
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if (hpet_enabled()) {
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cur_tick = hpet_get_ticks();
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if (hpet_enabled(s)) {
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cur_tick = hpet_get_ticks(s);
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} else {
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cur_tick = s->hpet_counter;
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}
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DPRINTF("qemu: reading counter = %" PRIx64 "\n", cur_tick);
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return cur_tick;
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case HPET_COUNTER + 4:
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if (hpet_enabled()) {
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cur_tick = hpet_get_ticks();
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if (hpet_enabled(s)) {
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cur_tick = hpet_get_ticks(s);
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} else {
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cur_tick = s->hpet_counter;
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}
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@ -457,7 +455,7 @@ static void hpet_ram_writel(void *opaque, target_phys_addr_t addr,
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(timer->period & 0xffffffff00000000ULL) | new_val;
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}
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timer->config &= ~HPET_TN_SETVAL;
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if (hpet_enabled()) {
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if (hpet_enabled(s)) {
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hpet_set_timer(timer);
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}
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break;
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@ -476,7 +474,7 @@ static void hpet_ram_writel(void *opaque, target_phys_addr_t addr,
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(timer->period & 0xffffffffULL) | new_val << 32;
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}
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timer->config &= ~HPET_TN_SETVAL;
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if (hpet_enabled()) {
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if (hpet_enabled(s)) {
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hpet_set_timer(timer);
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}
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break;
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@ -506,7 +504,7 @@ static void hpet_ram_writel(void *opaque, target_phys_addr_t addr,
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}
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} else if (deactivating_bit(old_val, new_val, HPET_CFG_ENABLE)) {
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/* Halt main counter and disable interrupt generation. */
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s->hpet_counter = hpet_get_ticks();
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s->hpet_counter = hpet_get_ticks(s);
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for (i = 0; i < HPET_NUM_TIMERS; i++) {
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hpet_del_timer(&s->timer[i]);
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}
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@ -527,7 +525,7 @@ static void hpet_ram_writel(void *opaque, target_phys_addr_t addr,
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/* FIXME: need to handle level-triggered interrupts */
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break;
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case HPET_COUNTER:
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if (hpet_enabled()) {
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if (hpet_enabled(s)) {
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DPRINTF("qemu: Writing counter while HPET enabled!\n");
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}
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s->hpet_counter =
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@ -536,7 +534,7 @@ static void hpet_ram_writel(void *opaque, target_phys_addr_t addr,
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value, s->hpet_counter);
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break;
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case HPET_COUNTER + 4:
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if (hpet_enabled()) {
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if (hpet_enabled(s)) {
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DPRINTF("qemu: Writing counter while HPET enabled!\n");
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}
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s->hpet_counter =
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@ -624,8 +622,6 @@ static int hpet_init(SysBusDevice *dev)
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int i, iomemtype;
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HPETTimer *timer;
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assert(!hpet_statep);
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hpet_statep = s;
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for (i = 0; i < HPET_NUM_IRQ_ROUTES; i++) {
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sysbus_init_irq(dev, &s->irqs[i]);
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}
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