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RISC-V: No traps on writes to misa,minstret,mcycle 

These fields are marked WARL (Write Any Values, Reads
Legal Values) in the RISC-V Privileged Architecture
Specification so instead of raising exceptions,
illegal writes are silently dropped.

Cc: Sagar Karandikar <sagark@eecs.berkeley.edu>
Cc: Bastian Koppelmann <kbastian@mail.uni-paderborn.de>
Cc: Palmer Dabbelt <palmer@sifive.com>
Cc: Alistair Francis <Alistair.Francis@wdc.com>
Signed-off-by: Michael Clark <mjc@sifive.com>
This commit is contained in:
Michael Clark 2018-03-06 10:33:31 +13:00
parent 1d1ee55274
commit b8643bd608
No known key found for this signature in database
GPG Key ID: 6BF1D7B357EF3E4F
1 changed files with 13 additions and 12 deletions
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25
target/riscv/op_helper.c
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@ -213,17 +213,19 @@ void csr_write_helper(CPURISCVState *env, target_ulong val_to_write,
break;
}
case CSR_MINSTRET:
qemu_log_mask(LOG_UNIMP, "CSR_MINSTRET: write not implemented");
goto do_illegal;
/* minstret is WARL so unsupported writes are ignored */
break;
case CSR_MCYCLE:
qemu_log_mask(LOG_UNIMP, "CSR_MCYCLE: write not implemented");
goto do_illegal;
/* mcycle is WARL so unsupported writes are ignored */
break;
#if defined(TARGET_RISCV32)
case CSR_MINSTRETH:
qemu_log_mask(LOG_UNIMP, "CSR_MINSTRETH: write not implemented");
goto do_illegal;
/* minstreth is WARL so unsupported writes are ignored */
break;
case CSR_MCYCLEH:
qemu_log_mask(LOG_UNIMP, "CSR_MCYCLEH: write not implemented");
goto do_illegal;
/* mcycleh is WARL so unsupported writes are ignored */
break;
#endif
case CSR_MUCOUNTEREN:
if (env->priv_ver <= PRIV_VERSION_1_09_1) {
env->scounteren = val_to_write;
@ -337,10 +339,9 @@ void csr_write_helper(CPURISCVState *env, target_ulong val_to_write,
case CSR_MBADADDR:
env->mbadaddr = val_to_write;
break;
case CSR_MISA: {
qemu_log_mask(LOG_UNIMP, "CSR_MISA: misa writes not supported");
goto do_illegal;
}
case CSR_MISA:
/* misa is WARL so unsupported writes are ignored */
break;
case CSR_PMPCFG0:
case CSR_PMPCFG1:
case CSR_PMPCFG2: