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target/arm: Convert Neon 2-reg-misc fp-compare-with-zero insns to decodetree 

Convert the fp-compare-with-zero insns in the Neon 2-reg-misc group to
decodetree.

Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
Reviewed-by: Richard Henderson <richard.henderson@linaro.org>
Message-id: 20200616170844.13318-17-peter.maydell@linaro.org
This commit is contained in:
Peter Maydell 2020-06-16 18:08:39 +01:00
parent 3e96b20528
commit baa59323e8
3 changed files with 39 additions and 45 deletions
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6
target/arm/neon-dp.decode
View File

@ -479,6 +479,12 @@ Vimm_1r 1111 001 . 1 . 000 ... .... cmode:4 0 . op:1 1 .... @1reg_imm
VABS 1111 001 11 . 11 .. 01 .... 0 0110 . . 0 .... @2misc
VNEG 1111 001 11 . 11 .. 01 .... 0 0111 . . 0 .... @2misc
VCGT0_F 1111 001 11 . 11 .. 01 .... 0 1000 . . 0 .... @2misc
VCGE0_F 1111 001 11 . 11 .. 01 .... 0 1001 . . 0 .... @2misc
VCEQ0_F 1111 001 11 . 11 .. 01 .... 0 1010 . . 0 .... @2misc
VCLE0_F 1111 001 11 . 11 .. 01 .... 0 1011 . . 0 .... @2misc
VCLT0_F 1111 001 11 . 11 .. 01 .... 0 1100 . . 0 .... @2misc
VABS_F 1111 001 11 . 11 .. 01 .... 0 1110 . . 0 .... @2misc
VNEG_F 1111 001 11 . 11 .. 01 .... 0 1111 . . 0 .... @2misc

28
target/arm/translate-neon.inc.c
View File

@ -3768,3 +3768,31 @@ static bool trans_VRINTX(DisasContext *s, arg_2misc *a)
}
return do_2misc_fp(s, a, gen_helper_rints_exact);
}
#define WRAP_FP_CMP0_FWD(WRAPNAME, FUNC) \
static void WRAPNAME(TCGv_i32 d, TCGv_i32 m, TCGv_ptr fpst) \
{ \
TCGv_i32 zero = tcg_const_i32(0); \
FUNC(d, m, zero, fpst); \
tcg_temp_free_i32(zero); \
}
#define WRAP_FP_CMP0_REV(WRAPNAME, FUNC) \
static void WRAPNAME(TCGv_i32 d, TCGv_i32 m, TCGv_ptr fpst) \
{ \
TCGv_i32 zero = tcg_const_i32(0); \
FUNC(d, zero, m, fpst); \
tcg_temp_free_i32(zero); \
}
#define DO_FP_CMP0(INSN, FUNC, REV) \
WRAP_FP_CMP0_##REV(gen_##INSN, FUNC) \
static bool trans_##INSN(DisasContext *s, arg_2misc *a) \
{ \
return do_2misc_fp(s, a, gen_##INSN); \
}
DO_FP_CMP0(VCGT0_F, gen_helper_neon_cgt_f32, FWD)
DO_FP_CMP0(VCGE0_F, gen_helper_neon_cge_f32, FWD)
DO_FP_CMP0(VCEQ0_F, gen_helper_neon_ceq_f32, FWD)
DO_FP_CMP0(VCLE0_F, gen_helper_neon_cge_f32, REV)
DO_FP_CMP0(VCLT0_F, gen_helper_neon_cgt_f32, REV)

50
target/arm/translate.c
View File

@ -4954,6 +4954,11 @@ static int disas_neon_data_insn(DisasContext *s, uint32_t insn)
case NEON_2RM_VCVT_SF:
case NEON_2RM_VCVT_UF:
case NEON_2RM_VRINTX:
case NEON_2RM_VCGT0_F:
case NEON_2RM_VCGE0_F:
case NEON_2RM_VCEQ0_F:
case NEON_2RM_VCLE0_F:
case NEON_2RM_VCLT0_F:
/* handled by decodetree */
return 1;
case NEON_2RM_VTRN:
@ -4975,51 +4980,6 @@ static int disas_neon_data_insn(DisasContext *s, uint32_t insn)
for (pass = 0; pass < (q ? 4 : 2); pass++) {
tmp = neon_load_reg(rm, pass);
switch (op) {
case NEON_2RM_VCGT0_F:
{
TCGv_ptr fpstatus = get_fpstatus_ptr(1);
tmp2 = tcg_const_i32(0);
gen_helper_neon_cgt_f32(tmp, tmp, tmp2, fpstatus);
tcg_temp_free_i32(tmp2);
tcg_temp_free_ptr(fpstatus);
break;
}
case NEON_2RM_VCGE0_F:
{
TCGv_ptr fpstatus = get_fpstatus_ptr(1);
tmp2 = tcg_const_i32(0);
gen_helper_neon_cge_f32(tmp, tmp, tmp2, fpstatus);
tcg_temp_free_i32(tmp2);
tcg_temp_free_ptr(fpstatus);
break;
}
case NEON_2RM_VCEQ0_F:
{
TCGv_ptr fpstatus = get_fpstatus_ptr(1);
tmp2 = tcg_const_i32(0);
gen_helper_neon_ceq_f32(tmp, tmp, tmp2, fpstatus);
tcg_temp_free_i32(tmp2);
tcg_temp_free_ptr(fpstatus);
break;
}
case NEON_2RM_VCLE0_F:
{
TCGv_ptr fpstatus = get_fpstatus_ptr(1);
tmp2 = tcg_const_i32(0);
gen_helper_neon_cge_f32(tmp, tmp2, tmp, fpstatus);
tcg_temp_free_i32(tmp2);
tcg_temp_free_ptr(fpstatus);
break;
}
case NEON_2RM_VCLT0_F:
{
TCGv_ptr fpstatus = get_fpstatus_ptr(1);
tmp2 = tcg_const_i32(0);
gen_helper_neon_cgt_f32(tmp, tmp2, tmp, fpstatus);
tcg_temp_free_i32(tmp2);
tcg_temp_free_ptr(fpstatus);
break;
}
case NEON_2RM_VSWP:
tmp2 = neon_load_reg(rd, pass);
neon_store_reg(rm, pass, tmp2);