mirror of https://gitee.com/openkylin/qemu.git
target-mips: add microMIPS exception handler support
Unlike MIPS16, microMIPS lets you choose the ISA mode for your exception handlers. The ISA mode is selectable via a user-writable CP0.Config3 flag. Signed-off-by: Nathan Froyd <froydnj@codesourcery.com> Signed-off-by: Aurelien Jarno <aurelien@aurel32.net>
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@ -363,6 +363,7 @@ struct CPUMIPSState {
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#define CP0C2_SA 0
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int32_t CP0_Config3;
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#define CP0C3_M 31
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#define CP0C3_ISA_ON_EXC 16
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#define CP0C3_DSPP 10
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#define CP0C3_LPA 7
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#define CP0C3_VEIC 6
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@ -385,6 +385,18 @@ static target_ulong exception_resume_pc (CPUState *env)
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return bad_pc;
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}
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static void set_hflags_for_handler (CPUState *env)
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{
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/* Exception handlers are entered in 32-bit mode. */
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env->hflags &= ~(MIPS_HFLAG_M16);
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/* ...except that microMIPS lets you choose. */
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if (env->insn_flags & ASE_MICROMIPS) {
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env->hflags |= (!!(env->CP0_Config3
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& (1 << CP0C3_ISA_ON_EXC))
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<< MIPS_HFLAG_M16_SHIFT);
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}
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}
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#endif
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void do_interrupt (CPUState *env)
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@ -440,8 +452,7 @@ void do_interrupt (CPUState *env)
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if (!(env->CP0_Status & (1 << CP0St_EXL)))
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env->CP0_Cause &= ~(1 << CP0Ca_BD);
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env->active_tc.PC = (int32_t)0xBFC00480;
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/* Exception handlers are entered in 32-bit mode. */
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env->hflags &= ~(MIPS_HFLAG_M16);
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set_hflags_for_handler(env);
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break;
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case EXCP_RESET:
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cpu_reset(env);
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@ -461,8 +472,7 @@ void do_interrupt (CPUState *env)
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if (!(env->CP0_Status & (1 << CP0St_EXL)))
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env->CP0_Cause &= ~(1 << CP0Ca_BD);
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env->active_tc.PC = (int32_t)0xBFC00000;
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/* Exception handlers are entered in 32-bit mode. */
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env->hflags &= ~(MIPS_HFLAG_M16);
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set_hflags_for_handler(env);
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break;
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case EXCP_EXT_INTERRUPT:
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cause = 0;
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@ -581,8 +591,7 @@ void do_interrupt (CPUState *env)
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env->active_tc.PC = (int32_t)(env->CP0_EBase & ~0x3ff);
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}
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env->active_tc.PC += offset;
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/* Exception handlers are entered in 32-bit mode. */
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env->hflags &= ~(MIPS_HFLAG_M16);
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set_hflags_for_handler(env);
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env->CP0_Cause = (env->CP0_Cause & ~(0x1f << CP0Ca_EC)) | (cause << CP0Ca_EC);
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break;
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default:
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