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hw/ide: Do ide_drive_get() within pci_ide_create_devs() 

The pci_ide_create_devs() function takes a hd_table parameter but all
callers just pass what ide_drive_get() returns so we can do it locally
simplifying callers and removing hd_table parameter.

Signed-off-by: BALATON Zoltan <balaton@eik.bme.hu>
Reviewed-by: Mark Cave-Ayland <mark.cave-ayland@ilande.co.uk>
Reviewed-by: Markus Armbruster <armbru@redhat.com>
Message-id: e9713fdded4d212fa68ed03b844e531934226a6f.1584457537.git.balaton@eik.bme.hu
Signed-off-by: John Snow <jsnow@redhat.com>
This commit is contained in:
BALATON Zoltan 2020-03-17 16:05:37 +01:00 committed by John Snow
parent 417adc2d50
commit be1765f398
9 changed files with 18 additions and 35 deletions
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11
hw/alpha/dp264.c
View File

@ -15,7 +15,6 @@
#include "qemu/error-report.h"
#include "sysemu/sysemu.h"
#include "hw/rtc/mc146818rtc.h"
#include "hw/ide.h"
#include "hw/ide/pci.h"
#include "hw/timer/i8254.h"
#include "hw/isa/superio.h"
@ -58,6 +57,7 @@ static void clipper_init(MachineState *machine)
const char *initrd_filename = machine->initrd_filename;
AlphaCPU *cpus[4];
PCIBus *pci_bus;
PCIDevice *pci_dev;
ISABus *isa_bus;
qemu_irq rtc_irq;
long size, i;
@ -100,15 +100,8 @@ static void clipper_init(MachineState *machine)
isa_create_simple(isa_bus, TYPE_SMC37C669_SUPERIO);
/* IDE disk setup. */
{
DriveInfo *hd[MAX_IDE_BUS * MAX_IDE_DEVS];
PCIDevice *pci_dev;
ide_drive_get(hd, ARRAY_SIZE(hd));
pci_dev = pci_create_simple(pci_bus, -1, "cmd646-ide");
pci_ide_create_devs(pci_dev, hd);
}
pci_ide_create_devs(pci_dev);
/* Load PALcode. Given that this is not "real" cpu palcode,
but one explicitly written for the emulation, we might as

9
hw/i386/pc_piix.c
View File

@ -86,7 +86,6 @@ static void pc_init1(MachineState *machine,
int piix3_devfn = -1;
qemu_irq smi_irq;
GSIState *gsi_state;
DriveInfo *hd[MAX_IDE_BUS * MAX_IDE_DEVS];
BusState *idebus[MAX_IDE_BUS];
ISADevice *rtc_state;
MemoryRegion *ram_memory;
@ -240,20 +239,22 @@ static void pc_init1(MachineState *machine,
pc_nic_init(pcmc, isa_bus, pci_bus);
ide_drive_get(hd, ARRAY_SIZE(hd));
if (pcmc->pci_enabled) {
PCIDevice *dev;
dev = pci_create_simple(pci_bus, piix3_devfn + 1,
xen_enabled() ? "piix3-ide-xen" : "piix3-ide");
pci_ide_create_devs(dev, hd);
pci_ide_create_devs(dev);
idebus[0] = qdev_get_child_bus(&dev->qdev, "ide.0");
idebus[1] = qdev_get_child_bus(&dev->qdev, "ide.1");
pc_cmos_init(pcms, idebus[0], idebus[1], rtc_state);
}
#ifdef CONFIG_IDE_ISA
else {
else {
DriveInfo *hd[MAX_IDE_BUS * MAX_IDE_DEVS];
int i;
ide_drive_get(hd, ARRAY_SIZE(hd));
for (i = 0; i < MAX_IDE_BUS; i++) {
ISADevice *dev;
char busname[] = "ide.0";

4
hw/ide/pci.c
View File

@ -477,13 +477,15 @@ const VMStateDescription vmstate_ide_pci = {
};
/* hd_table must contain 4 block drivers */
void pci_ide_create_devs(PCIDevice *dev, DriveInfo **hd_table)
void pci_ide_create_devs(PCIDevice *dev)
{
PCIIDEState *d = PCI_IDE(dev);
DriveInfo *hd_table[2 * MAX_IDE_DEVS];
static const int bus[4] = { 0, 0, 1, 1 };
static const int unit[4] = { 0, 1, 0, 1 };
int i;
ide_drive_get(hd_table, ARRAY_SIZE(hd_table));
for (i = 0; i < 4; i++) {
if (hd_table[i]) {
ide_create_drive(d->bus + bus[i], unit[i], hd_table[i]);

10
hw/isa/piix4.c
View File

@ -241,11 +241,8 @@ static void piix4_register_types(void)
type_init(piix4_register_types)
DeviceState *piix4_create(PCIBus *pci_bus, ISABus **isa_bus,
I2CBus **smbus, size_t ide_buses)
DeviceState *piix4_create(PCIBus *pci_bus, ISABus **isa_bus, I2CBus **smbus)
{
size_t ide_drives = ide_buses * MAX_IDE_DEVS;
DriveInfo **hd;
PCIDevice *pci;
DeviceState *dev;
int devfn = PCI_DEVFN(10, 0);
@ -258,10 +255,7 @@ DeviceState *piix4_create(PCIBus *pci_bus, ISABus **isa_bus,
}
pci = pci_create_simple(pci_bus, devfn + 1, "piix4-ide");
hd = g_new(DriveInfo *, ide_drives);
ide_drive_get(hd, ide_drives);
pci_ide_create_devs(pci, hd);
g_free(hd);
pci_ide_create_devs(pci);
pci_create_simple(pci_bus, devfn + 2, "piix4-usb-uhci");
if (smbus) {

4
hw/mips/mips_fulong2e.c
View File

@ -239,7 +239,6 @@ static void vt82c686b_southbridge_init(PCIBus *pci_bus, int slot, qemu_irq intc,
{
qemu_irq *i8259;
ISABus *isa_bus;
DriveInfo *hd[MAX_IDE_BUS * MAX_IDE_DEVS];
PCIDevice *dev;
isa_bus = vt82c686b_isa_init(pci_bus, PCI_DEVFN(slot, 0));
@ -259,8 +258,7 @@ static void vt82c686b_southbridge_init(PCIBus *pci_bus, int slot, qemu_irq intc,
isa_create_simple(isa_bus, TYPE_VT82C686B_SUPERIO);
dev = pci_create_simple(pci_bus, PCI_DEVFN(slot, 1), "via-ide");
ide_drive_get(hd, ARRAY_SIZE(hd));
pci_ide_create_devs(dev, hd);
pci_ide_create_devs(dev);
pci_create_simple(pci_bus, PCI_DEVFN(slot, 2), "vt82c686b-usb-uhci");
pci_create_simple(pci_bus, PCI_DEVFN(slot, 3), "vt82c686b-usb-uhci");

2
hw/mips/mips_malta.c
View File

@ -1403,7 +1403,7 @@ void mips_malta_init(MachineState *machine)
pci_bus = gt64120_register(s->i8259);
/* Southbridge */
dev = piix4_create(pci_bus, &isa_bus, &smbus, MAX_IDE_BUS);
dev = piix4_create(pci_bus, &isa_bus, &smbus);
/* Interrupt controller */
qdev_connect_gpio_out_named(dev, "intr", 0, i8259_irq);

6
hw/sparc64/sun4u.c
View File

@ -50,7 +50,6 @@
#include "hw/sparc/sparc64.h"
#include "hw/nvram/fw_cfg.h"
#include "hw/sysbus.h"
#include "hw/ide.h"
#include "hw/ide/pci.h"
#include "hw/loader.h"
#include "hw/fw-path-provider.h"
@ -563,7 +562,6 @@ static void sun4uv_init(MemoryRegion *address_space_mem,
PCIBus *pci_bus, *pci_busA, *pci_busB;
PCIDevice *ebus, *pci_dev;
SysBusDevice *s;
DriveInfo *hd[MAX_IDE_BUS * MAX_IDE_DEVS];
DeviceState *iommu, *dev;
FWCfgState *fw_cfg;
NICInfo *nd;
@ -663,12 +661,10 @@ static void sun4uv_init(MemoryRegion *address_space_mem,
qemu_macaddr_default_if_unset(&macaddr);
}
ide_drive_get(hd, ARRAY_SIZE(hd));
pci_dev = pci_create(pci_busA, PCI_DEVFN(3, 0), "cmd646-ide");
qdev_prop_set_uint32(&pci_dev->qdev, "secondary", 1);
qdev_init_nofail(&pci_dev->qdev);
pci_ide_create_devs(pci_dev, hd);
pci_ide_create_devs(pci_dev);
/* Map NVRAM into I/O (ebus) space */
nvram = m48t59_init(NULL, 0, 0, NVRAM_SIZE, 1968, 59);

2
include/hw/ide/pci.h
View File

@ -63,7 +63,7 @@ static inline IDEState *bmdma_active_if(BMDMAState *bmdma)
void bmdma_init(IDEBus *bus, BMDMAState *bm, PCIIDEState *d);
void bmdma_cmd_writeb(BMDMAState *bm, uint32_t val);
extern MemoryRegionOps bmdma_addr_ioport_ops;
void pci_ide_create_devs(PCIDevice *dev, DriveInfo **hd_table);
void pci_ide_create_devs(PCIDevice *dev);
extern const VMStateDescription vmstate_ide_pci;
extern const MemoryRegionOps pci_ide_cmd_le_ops;

3
include/hw/southbridge/piix.h
View File

@ -68,7 +68,6 @@ extern PCIDevice *piix4_dev;
PIIX3State *piix3_create(PCIBus *pci_bus, ISABus **isa_bus);
DeviceState *piix4_create(PCIBus *pci_bus, ISABus **isa_bus,
I2CBus **smbus, size_t ide_buses);
DeviceState *piix4_create(PCIBus *pci_bus, ISABus **isa_bus, I2CBus **smbus);
#endif