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microblaze_boot: Pass MicroBlazeCPU to microblaze_load_kernel() 

Allows us to use cpu_reset() in place of cpu_state_reset() in
main_cpu_reset().

Also pass it through to its reset callbacks, while at it.

Signed-off-by: Andreas Färber <afaerber@suse.de>
Acked-by: Edgar E. Iglesias <edgar.iglesias@gmail.com>
This commit is contained in:
Andreas Färber 2012-05-05 12:30:53 +02:00
parent 3ed607333e
commit bf494367fa
4 changed files with 18 additions and 14 deletions

16
hw/microblaze_boot.c
View File

@ -35,7 +35,7 @@
static struct
{
void (*machine_cpu_reset)(CPUMBState *);
void (*machine_cpu_reset)(MicroBlazeCPU *);
uint32_t bootstrap_pc;
uint32_t cmdline;
uint32_t fdt;
@ -43,14 +43,15 @@ static struct
static void main_cpu_reset(void *opaque)
{
CPUMBState *env = opaque;
MicroBlazeCPU *cpu = opaque;
CPUMBState *env = &cpu->env;
cpu_state_reset(env);
cpu_reset(CPU(cpu));
env->regs[5] = boot_info.cmdline;
env->regs[7] = boot_info.fdt;
env->sregs[SR_PC] = boot_info.bootstrap_pc;
if (boot_info.machine_cpu_reset) {
boot_info.machine_cpu_reset(env);
boot_info.machine_cpu_reset(cpu);
}
}
@ -99,11 +100,10 @@ static uint64_t translate_kernel_address(void *opaque, uint64_t addr)
return addr - 0x30000000LL;
}
void microblaze_load_kernel(CPUMBState *env, target_phys_addr_t ddr_base,
void microblaze_load_kernel(MicroBlazeCPU *cpu, target_phys_addr_t ddr_base,
uint32_t ramsize, const char *dtb_filename,
void (*machine_cpu_reset)(CPUMBState *))
void (*machine_cpu_reset)(MicroBlazeCPU *))
{
QemuOpts *machine_opts;
const char *kernel_filename = NULL;
const char *kernel_cmdline = NULL;
@ -122,7 +122,7 @@ void microblaze_load_kernel(CPUMBState *env, target_phys_addr_t ddr_base,
}
boot_info.machine_cpu_reset = machine_cpu_reset;
qemu_register_reset(main_cpu_reset, env);
qemu_register_reset(main_cpu_reset, cpu);
if (kernel_filename) {
int kernel_size;

4
hw/microblaze_boot.h
View File

@ -3,8 +3,8 @@
#include "hw.h"
void microblaze_load_kernel(CPUMBState *env, target_phys_addr_t ddr_base,
void microblaze_load_kernel(MicroBlazeCPU *cpu, target_phys_addr_t ddr_base,
uint32_t ramsize, const char *dtb_filename,
void (*machine_cpu_reset)(CPUMBState *));
void (*machine_cpu_reset)(MicroBlazeCPU *));
#endif /* __MICROBLAZE_BOOT __ */

6
hw/petalogix_ml605_mmu.c
View File

@ -54,8 +54,10 @@
#define AXIENET_BASEADDR 0x82780000
#define AXIDMA_BASEADDR 0x84600000
static void machine_cpu_reset(CPUMBState *env)
static void machine_cpu_reset(MicroBlazeCPU *cpu)
{
CPUMBState *env = &cpu->env;
env->pvr.regs[10] = 0x0e000000; /* virtex 6 */
/* setup pvr to match kernel setting */
env->pvr.regs[5] |= PVR5_DCACHE_WRITEBACK_MASK;
@ -133,7 +135,7 @@ petalogix_ml605_init(ram_addr_t ram_size,
irq[1], irq[0], 100 * 1000000);
}
microblaze_load_kernel(env, ddr_base, ram_size, BINARY_DEVICE_TREE_FILE,
microblaze_load_kernel(cpu, ddr_base, ram_size, BINARY_DEVICE_TREE_FILE,
machine_cpu_reset);
}

6
hw/petalogix_s3adsp1800_mmu.c
View File

@ -49,8 +49,10 @@
#define UARTLITE_BASEADDR 0x84000000
#define ETHLITE_BASEADDR 0x81000000
static void machine_cpu_reset(CPUMBState *env)
static void machine_cpu_reset(MicroBlazeCPU *cpu)
{
CPUMBState *env = &cpu->env;
env->pvr.regs[10] = 0x0c000000; /* spartan 3a dsp family. */
}
@ -107,7 +109,7 @@ petalogix_s3adsp1800_init(ram_addr_t ram_size,
xilinx_timer_create(TIMER_BASEADDR, irq[0], 2, 62 * 1000000);
xilinx_ethlite_create(&nd_table[0], ETHLITE_BASEADDR, irq[1], 0, 0);
microblaze_load_kernel(env, ddr_base, ram_size,
microblaze_load_kernel(cpu, ddr_base, ram_size,
BINARY_DEVICE_TREE_FILE, machine_cpu_reset);
}