mirror of https://gitee.com/openkylin/qemu.git
ppc/pnv: fix XSCOM core addressing on POWER9
The XSCOM base address of the core chiplet was wrongly calculated. Use the OPAL macros to fix that and do a couple of renames. Signed-off-by: Cédric Le Goater <clg@kaod.org> Signed-off-by: David Gibson <david@gibson.dropbear.id.au>
This commit is contained in:
parent
b3b066e9d8
commit
c035851ac0
15
hw/ppc/pnv.c
15
hw/ppc/pnv.c
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@ -721,7 +721,6 @@ static void pnv_chip_power8e_class_init(ObjectClass *klass, void *data)
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k->cores_mask = POWER8E_CORE_MASK;
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k->cores_mask = POWER8E_CORE_MASK;
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k->core_pir = pnv_chip_core_pir_p8;
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k->core_pir = pnv_chip_core_pir_p8;
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k->xscom_base = 0x003fc0000000000ull;
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k->xscom_base = 0x003fc0000000000ull;
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k->xscom_core_base = 0x10000000ull;
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dc->desc = "PowerNV Chip POWER8E";
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dc->desc = "PowerNV Chip POWER8E";
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}
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}
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@ -735,7 +734,6 @@ static void pnv_chip_power8_class_init(ObjectClass *klass, void *data)
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k->cores_mask = POWER8_CORE_MASK;
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k->cores_mask = POWER8_CORE_MASK;
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k->core_pir = pnv_chip_core_pir_p8;
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k->core_pir = pnv_chip_core_pir_p8;
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k->xscom_base = 0x003fc0000000000ull;
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k->xscom_base = 0x003fc0000000000ull;
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k->xscom_core_base = 0x10000000ull;
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dc->desc = "PowerNV Chip POWER8";
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dc->desc = "PowerNV Chip POWER8";
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}
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}
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@ -749,7 +747,6 @@ static void pnv_chip_power8nvl_class_init(ObjectClass *klass, void *data)
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k->cores_mask = POWER8_CORE_MASK;
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k->cores_mask = POWER8_CORE_MASK;
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k->core_pir = pnv_chip_core_pir_p8;
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k->core_pir = pnv_chip_core_pir_p8;
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k->xscom_base = 0x003fc0000000000ull;
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k->xscom_base = 0x003fc0000000000ull;
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k->xscom_core_base = 0x10000000ull;
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dc->desc = "PowerNV Chip POWER8NVL";
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dc->desc = "PowerNV Chip POWER8NVL";
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}
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}
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@ -763,7 +760,6 @@ static void pnv_chip_power9_class_init(ObjectClass *klass, void *data)
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k->cores_mask = POWER9_CORE_MASK;
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k->cores_mask = POWER9_CORE_MASK;
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k->core_pir = pnv_chip_core_pir_p9;
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k->core_pir = pnv_chip_core_pir_p9;
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k->xscom_base = 0x00603fc00000000ull;
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k->xscom_base = 0x00603fc00000000ull;
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k->xscom_core_base = 0x0ull;
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dc->desc = "PowerNV Chip POWER9";
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dc->desc = "PowerNV Chip POWER9";
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}
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}
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@ -887,6 +883,7 @@ static void pnv_chip_realize(DeviceState *dev, Error **errp)
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&& (i < chip->nr_cores); core_hwid++) {
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&& (i < chip->nr_cores); core_hwid++) {
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char core_name[32];
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char core_name[32];
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void *pnv_core = chip->cores + i * typesize;
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void *pnv_core = chip->cores + i * typesize;
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uint64_t xscom_core_base;
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if (!(chip->cores_mask & (1ull << core_hwid))) {
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if (!(chip->cores_mask & (1ull << core_hwid))) {
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continue;
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continue;
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@ -910,9 +907,13 @@ static void pnv_chip_realize(DeviceState *dev, Error **errp)
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object_unref(OBJECT(pnv_core));
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object_unref(OBJECT(pnv_core));
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/* Each core has an XSCOM MMIO region */
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/* Each core has an XSCOM MMIO region */
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pnv_xscom_add_subregion(chip,
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if (!pnv_chip_is_power9(chip)) {
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PNV_XSCOM_EX_CORE_BASE(pcc->xscom_core_base,
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xscom_core_base = PNV_XSCOM_EX_BASE(core_hwid);
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core_hwid),
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} else {
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xscom_core_base = PNV_XSCOM_P9_EC_BASE(core_hwid);
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}
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pnv_xscom_add_subregion(chip, xscom_core_base,
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&PNV_CORE(pnv_core)->xscom_regs);
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&PNV_CORE(pnv_core)->xscom_regs);
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i++;
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i++;
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}
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}
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@ -192,7 +192,7 @@ static void pnv_core_realize(DeviceState *dev, Error **errp)
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snprintf(name, sizeof(name), "xscom-core.%d", cc->core_id);
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snprintf(name, sizeof(name), "xscom-core.%d", cc->core_id);
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pnv_xscom_region_init(&pc->xscom_regs, OBJECT(dev), &pnv_core_xscom_ops,
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pnv_xscom_region_init(&pc->xscom_regs, OBJECT(dev), &pnv_core_xscom_ops,
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pc, name, PNV_XSCOM_EX_CORE_SIZE);
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pc, name, PNV_XSCOM_EX_SIZE);
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return;
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return;
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err:
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err:
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@ -74,7 +74,6 @@ typedef struct PnvChipClass {
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uint64_t cores_mask;
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uint64_t cores_mask;
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hwaddr xscom_base;
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hwaddr xscom_base;
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hwaddr xscom_core_base;
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uint32_t (*core_pir)(PnvChip *chip, uint32_t core_id);
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uint32_t (*core_pir)(PnvChip *chip, uint32_t core_id);
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} PnvChipClass;
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} PnvChipClass;
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@ -21,6 +21,8 @@
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#include "qom/object.h"
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#include "qom/object.h"
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typedef struct PnvChip PnvChip;
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typedef struct PnvXScomInterface {
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typedef struct PnvXScomInterface {
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Object parent;
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Object parent;
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} PnvXScomInterface;
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} PnvXScomInterface;
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@ -54,8 +56,15 @@ typedef struct PnvXScomInterfaceClass {
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* PCB SLAVE 0x110Fxxxx
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* PCB SLAVE 0x110Fxxxx
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*/
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*/
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#define PNV_XSCOM_EX_CORE_BASE(base, i) ((base) | ((uint64_t)(i) << 24))
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#define PNV_XSCOM_EX_CORE_BASE 0x10000000ull
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#define PNV_XSCOM_EX_CORE_SIZE 0x100000
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#define PNV_XSCOM_EX_BASE(core) \
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(PNV_XSCOM_EX_CORE_BASE | ((uint64_t)(core) << 24))
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#define PNV_XSCOM_EX_SIZE 0x100000
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#define PNV_XSCOM_P9_EC_BASE(core) \
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((uint64_t)(((core) & 0x1F) + 0x20) << 24)
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#define PNV_XSCOM_P9_EC_SIZE 0x100000
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#define PNV_XSCOM_LPC_BASE 0xb0020
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#define PNV_XSCOM_LPC_BASE 0xb0020
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#define PNV_XSCOM_LPC_SIZE 0x4
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#define PNV_XSCOM_LPC_SIZE 0x4
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@ -21,7 +21,6 @@ typedef struct PnvChip {
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PnvChipType chip_type;
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PnvChipType chip_type;
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const char *cpu_model;
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const char *cpu_model;
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uint64_t xscom_base;
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uint64_t xscom_base;
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uint64_t xscom_core_base;
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uint64_t cfam_id;
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uint64_t cfam_id;
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uint32_t first_core;
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uint32_t first_core;
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} PnvChip;
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} PnvChip;
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@ -31,14 +30,12 @@ static const PnvChip pnv_chips[] = {
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.chip_type = PNV_CHIP_POWER8,
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.chip_type = PNV_CHIP_POWER8,
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.cpu_model = "POWER8",
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.cpu_model = "POWER8",
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.xscom_base = 0x0003fc0000000000ull,
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.xscom_base = 0x0003fc0000000000ull,
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.xscom_core_base = 0x10000000ull,
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.cfam_id = 0x220ea04980000000ull,
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.cfam_id = 0x220ea04980000000ull,
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.first_core = 0x1,
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.first_core = 0x1,
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}, {
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}, {
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.chip_type = PNV_CHIP_POWER8NVL,
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.chip_type = PNV_CHIP_POWER8NVL,
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.cpu_model = "POWER8NVL",
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.cpu_model = "POWER8NVL",
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.xscom_base = 0x0003fc0000000000ull,
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.xscom_base = 0x0003fc0000000000ull,
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.xscom_core_base = 0x10000000ull,
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.cfam_id = 0x120d304980000000ull,
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.cfam_id = 0x120d304980000000ull,
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.first_core = 0x1,
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.first_core = 0x1,
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},
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},
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@ -47,7 +44,6 @@ static const PnvChip pnv_chips[] = {
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.chip_type = PNV_CHIP_POWER9,
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.chip_type = PNV_CHIP_POWER9,
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.cpu_model = "POWER9",
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.cpu_model = "POWER9",
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.xscom_base = 0x000603fc00000000ull,
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.xscom_base = 0x000603fc00000000ull,
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.xscom_core_base = 0x0ull,
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.cfam_id = 0x220d104900008000ull,
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.cfam_id = 0x220d104900008000ull,
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.first_core = 0x0,
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.first_core = 0x0,
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},
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},
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@ -89,16 +85,27 @@ static void test_cfam_id(const void *data)
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qtest_quit(global_qtest);
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qtest_quit(global_qtest);
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}
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}
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#define PNV_XSCOM_EX_CORE_BASE(chip, i) \
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((chip)->xscom_core_base | (((uint64_t)i) << 24))
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#define PNV_XSCOM_EX_CORE_BASE 0x10000000ull
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#define PNV_XSCOM_EX_BASE(core) \
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(PNV_XSCOM_EX_CORE_BASE | ((uint64_t)(core) << 24))
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#define PNV_XSCOM_P9_EC_BASE(core) \
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((uint64_t)(((core) & 0x1F) + 0x20) << 24)
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#define PNV_XSCOM_EX_DTS_RESULT0 0x50000
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#define PNV_XSCOM_EX_DTS_RESULT0 0x50000
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static void test_xscom_core(const PnvChip *chip)
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static void test_xscom_core(const PnvChip *chip)
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{
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{
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uint32_t first_core_dts0 =
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uint32_t first_core_dts0 = PNV_XSCOM_EX_DTS_RESULT0;
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PNV_XSCOM_EX_CORE_BASE(chip, chip->first_core) |
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uint64_t dts0;
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PNV_XSCOM_EX_DTS_RESULT0;
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uint64_t dts0 = pnv_xscom_read(chip, first_core_dts0);
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if (chip->chip_type != PNV_CHIP_POWER9) {
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first_core_dts0 |= PNV_XSCOM_EX_BASE(chip->first_core);
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} else {
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first_core_dts0 |= PNV_XSCOM_P9_EC_BASE(chip->first_core);
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}
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dts0 = pnv_xscom_read(chip, first_core_dts0);
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g_assert_cmphex(dts0, ==, 0x26f024f023f0000ull);
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g_assert_cmphex(dts0, ==, 0x26f024f023f0000ull);
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}
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}
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