mirror of https://gitee.com/openkylin/qemu.git
hw/nvram/nrf51_nvm: Add nRF51 non-volatile memories
The nRF51 contains three regions of non-volatile memory (NVM):
- CODE (R/W): contains code
- FICR (R): Factory information like code size, chip id etc.
- UICR (R/W): Changeable configuration data. Lock bits, Code
protection configuration, Bootloader address, Nordic SoftRadio
configuration, Firmware configuration.
Read and write access to the memories is managed by the
Non-volatile memory controller.
Memory schema:
[ CPU ] -+- [ NVM, either FICR, UICR or CODE ]
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\- [ NVMC ]
Signed-off-by: Steffen Görtz <contrib@steffen-goertz.de>
Signed-off-by: Stefan Hajnoczi <stefanha@redhat.com>
Tested-by: Joel Stanley <joel@jms.id.au>
Reviewed-by: Peter Maydell <peter.maydell@linaro.org>
Message-id: 20190201023357.22596-2-stefanha@redhat.com
Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
This commit is contained in:
Steffen Görtz
Peter Maydell
parent
1cf86a8618
commit
c0d4eb8352
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@ -5,3 +5,4 @@ common-obj-y += fw_cfg.o
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common-obj-y += chrp_nvram.o
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common-obj-$(CONFIG_MAC_NVRAM) += mac_nvram.o
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obj-$(CONFIG_PSERIES) += spapr_nvram.o
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obj-$(CONFIG_NRF51_SOC) += nrf51_nvm.o
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@ -0,0 +1,388 @@
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/*
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* Nordic Semiconductor nRF51 non-volatile memory
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*
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* It provides an interface to erase regions in flash memory.
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* Furthermore it provides the user and factory information registers.
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*
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* Reference Manual: http://infocenter.nordicsemi.com/pdf/nRF51_RM_v3.0.pdf
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*
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* See nRF51 reference manual and product sheet sections:
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* + Non-Volatile Memory Controller (NVMC)
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* + Factory Information Configuration Registers (FICR)
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* + User Information Configuration Registers (UICR)
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*
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* Copyright 2018 Steffen Görtz <contrib@steffen-goertz.de>
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*
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* This code is licensed under the GPL version 2 or later. See
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* the COPYING file in the top-level directory.
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*/
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#include "qemu/osdep.h"
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#include "qapi/error.h"
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#include "qemu/log.h"
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#include "exec/address-spaces.h"
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#include "hw/arm/nrf51.h"
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#include "hw/nvram/nrf51_nvm.h"
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/*
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* FICR Registers Assignments
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* CODEPAGESIZE 0x010
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* CODESIZE 0x014
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* CLENR0 0x028
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* PPFC 0x02C
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* NUMRAMBLOCK 0x034
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* SIZERAMBLOCKS 0x038
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* SIZERAMBLOCK[0] 0x038
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* SIZERAMBLOCK[1] 0x03C
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* SIZERAMBLOCK[2] 0x040
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* SIZERAMBLOCK[3] 0x044
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* CONFIGID 0x05C
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* DEVICEID[0] 0x060
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* DEVICEID[1] 0x064
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* ER[0] 0x080
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* ER[1] 0x084
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* ER[2] 0x088
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* ER[3] 0x08C
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* IR[0] 0x090
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* IR[1] 0x094
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* IR[2] 0x098
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* IR[3] 0x09C
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* DEVICEADDRTYPE 0x0A0
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* DEVICEADDR[0] 0x0A4
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* DEVICEADDR[1] 0x0A8
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* OVERRIDEEN 0x0AC
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* NRF_1MBIT[0] 0x0B0
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* NRF_1MBIT[1] 0x0B4
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* NRF_1MBIT[2] 0x0B8
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* NRF_1MBIT[3] 0x0BC
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* NRF_1MBIT[4] 0x0C0
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* BLE_1MBIT[0] 0x0EC
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* BLE_1MBIT[1] 0x0F0
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* BLE_1MBIT[2] 0x0F4
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* BLE_1MBIT[3] 0x0F8
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* BLE_1MBIT[4] 0x0FC
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*/
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static const uint32_t ficr_content[64] = {
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0xFFFFFFFF, 0xFFFFFFFF, 0xFFFFFFFF, 0xFFFFFFFF, 0x00000400,
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0x00000100, 0xFFFFFFFF, 0xFFFFFFFF, 0x00000002, 0x00002000,
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0x00002000, 0x00002000, 0xFFFFFFFF, 0xFFFFFFFF, 0xFFFFFFFF,
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0xFFFFFFFF, 0xFFFFFFFF, 0xFFFFFFFF, 0xFFFFFFFF, 0xFFFFFFFF,
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0xFFFFFFFF, 0xFFFFFFFF, 0xFFFFFFFF, 0xFFFFFFFF, 0x00000003,
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0x12345678, 0x9ABCDEF1, 0xFFFFFFFF, 0xFFFFFFFF, 0xFFFFFFFF,
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0xFFFFFFFF, 0xFFFFFFFF, 0xFFFFFFFF, 0xFFFFFFFF, 0xFFFFFFFF,
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0xFFFFFFFF, 0xFFFFFFFF, 0xFFFFFFFF, 0xFFFFFFFF, 0xFFFFFFFF,
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0xFFFFFFFF, 0xFFFFFFFF, 0xFFFFFFFF, 0xFFFFFFFF, 0xFFFFFFFF,
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0xFFFFFFFF, 0xFFFFFFFF, 0xFFFFFFFF, 0xFFFFFFFF, 0xFFFFFFFF,
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0xFFFFFFFF, 0xFFFFFFFF, 0xFFFFFFFF, 0xFFFFFFFF, 0xFFFFFFFF,
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0xFFFFFFFF, 0xFFFFFFFF, 0xFFFFFFFF, 0xFFFFFFFF, 0xFFFFFFFF,
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0xFFFFFFFF, 0xFFFFFFFF, 0xFFFFFFFF, 0xFFFFFFFF
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};
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static uint64_t ficr_read(void *opaque, hwaddr offset, unsigned int size)
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{
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assert(offset < sizeof(ficr_content));
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return ficr_content[offset / 4];
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}
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static void ficr_write(void *opaque, hwaddr offset, uint64_t value,
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unsigned int size)
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{
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/* Intentionally do nothing */
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}
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static const MemoryRegionOps ficr_ops = {
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.read = ficr_read,
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.write = ficr_write,
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.impl.min_access_size = 4,
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.impl.max_access_size = 4,
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.endianness = DEVICE_LITTLE_ENDIAN
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};
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/*
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* UICR Registers Assignments
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* CLENR0 0x000
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* RBPCONF 0x004
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* XTALFREQ 0x008
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* FWID 0x010
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* BOOTLOADERADDR 0x014
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* NRFFW[0] 0x014
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* NRFFW[1] 0x018
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* NRFFW[2] 0x01C
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* NRFFW[3] 0x020
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* NRFFW[4] 0x024
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* NRFFW[5] 0x028
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* NRFFW[6] 0x02C
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* NRFFW[7] 0x030
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* NRFFW[8] 0x034
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* NRFFW[9] 0x038
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* NRFFW[10] 0x03C
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* NRFFW[11] 0x040
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* NRFFW[12] 0x044
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* NRFFW[13] 0x048
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* NRFFW[14] 0x04C
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* NRFHW[0] 0x050
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* NRFHW[1] 0x054
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* NRFHW[2] 0x058
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* NRFHW[3] 0x05C
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* NRFHW[4] 0x060
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* NRFHW[5] 0x064
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* NRFHW[6] 0x068
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* NRFHW[7] 0x06C
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* NRFHW[8] 0x070
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* NRFHW[9] 0x074
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* NRFHW[10] 0x078
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* NRFHW[11] 0x07C
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* CUSTOMER[0] 0x080
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* CUSTOMER[1] 0x084
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* CUSTOMER[2] 0x088
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* CUSTOMER[3] 0x08C
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* CUSTOMER[4] 0x090
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* CUSTOMER[5] 0x094
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* CUSTOMER[6] 0x098
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* CUSTOMER[7] 0x09C
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* CUSTOMER[8] 0x0A0
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* CUSTOMER[9] 0x0A4
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* CUSTOMER[10] 0x0A8
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* CUSTOMER[11] 0x0AC
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* CUSTOMER[12] 0x0B0
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* CUSTOMER[13] 0x0B4
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* CUSTOMER[14] 0x0B8
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* CUSTOMER[15] 0x0BC
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* CUSTOMER[16] 0x0C0
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* CUSTOMER[17] 0x0C4
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* CUSTOMER[18] 0x0C8
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* CUSTOMER[19] 0x0CC
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* CUSTOMER[20] 0x0D0
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* CUSTOMER[21] 0x0D4
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* CUSTOMER[22] 0x0D8
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* CUSTOMER[23] 0x0DC
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* CUSTOMER[24] 0x0E0
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* CUSTOMER[25] 0x0E4
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* CUSTOMER[26] 0x0E8
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* CUSTOMER[27] 0x0EC
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* CUSTOMER[28] 0x0F0
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* CUSTOMER[29] 0x0F4
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* CUSTOMER[30] 0x0F8
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* CUSTOMER[31] 0x0FC
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*/
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static uint64_t uicr_read(void *opaque, hwaddr offset, unsigned int size)
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{
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NRF51NVMState *s = NRF51_NVM(opaque);
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assert(offset < sizeof(s->uicr_content));
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return s->uicr_content[offset / 4];
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}
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static void uicr_write(void *opaque, hwaddr offset, uint64_t value,
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unsigned int size)
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{
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NRF51NVMState *s = NRF51_NVM(opaque);
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assert(offset < sizeof(s->uicr_content));
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s->uicr_content[offset / 4] = value;
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}
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static const MemoryRegionOps uicr_ops = {
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.read = uicr_read,
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.write = uicr_write,
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.impl.min_access_size = 4,
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.impl.max_access_size = 4,
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.endianness = DEVICE_LITTLE_ENDIAN
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};
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static uint64_t io_read(void *opaque, hwaddr offset, unsigned int size)
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{
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NRF51NVMState *s = NRF51_NVM(opaque);
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uint64_t r = 0;
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switch (offset) {
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case NRF51_NVMC_READY:
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r = NRF51_NVMC_READY_READY;
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break;
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case NRF51_NVMC_CONFIG:
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r = s->config;
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break;
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default:
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qemu_log_mask(LOG_GUEST_ERROR,
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"%s: bad read offset 0x%" HWADDR_PRIx "\n", __func__, offset);
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break;
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}
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return r;
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}
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static void io_write(void *opaque, hwaddr offset, uint64_t value,
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unsigned int size)
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{
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NRF51NVMState *s = NRF51_NVM(opaque);
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switch (offset) {
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case NRF51_NVMC_CONFIG:
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s->config = value & NRF51_NVMC_CONFIG_MASK;
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break;
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case NRF51_NVMC_ERASEPCR0:
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case NRF51_NVMC_ERASEPCR1:
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if (s->config & NRF51_NVMC_CONFIG_EEN) {
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/* Mask in-page sub address */
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value &= ~(NRF51_PAGE_SIZE - 1);
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if (value <= (s->flash_size - NRF51_PAGE_SIZE)) {
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memset(s->storage + value, 0xFF, NRF51_PAGE_SIZE);
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memory_region_flush_rom_device(&s->flash, value,
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NRF51_PAGE_SIZE);
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}
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} else {
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qemu_log_mask(LOG_GUEST_ERROR,
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"%s: Flash erase at 0x%" HWADDR_PRIx" while flash not erasable.\n",
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__func__, offset);
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}
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break;
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case NRF51_NVMC_ERASEALL:
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if (value == NRF51_NVMC_ERASE) {
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if (s->config & NRF51_NVMC_CONFIG_EEN) {
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memset(s->storage, 0xFF, s->flash_size);
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memory_region_flush_rom_device(&s->flash, 0, s->flash_size);
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memset(s->uicr_content, 0xFF, sizeof(s->uicr_content));
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} else {
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qemu_log_mask(LOG_GUEST_ERROR, "%s: Flash not erasable.\n",
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__func__);
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}
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}
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break;
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case NRF51_NVMC_ERASEUICR:
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if (value == NRF51_NVMC_ERASE) {
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memset(s->uicr_content, 0xFF, sizeof(s->uicr_content));
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}
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break;
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default:
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qemu_log_mask(LOG_GUEST_ERROR,
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"%s: bad write offset 0x%" HWADDR_PRIx "\n", __func__, offset);
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}
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}
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static const MemoryRegionOps io_ops = {
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.read = io_read,
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.write = io_write,
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.impl.min_access_size = 4,
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.impl.max_access_size = 4,
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.endianness = DEVICE_LITTLE_ENDIAN,
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};
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static void flash_write(void *opaque, hwaddr offset, uint64_t value,
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unsigned int size)
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{
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NRF51NVMState *s = NRF51_NVM(opaque);
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if (s->config & NRF51_NVMC_CONFIG_WEN) {
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uint32_t oldval;
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assert(offset + size <= s->flash_size);
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/* NOR Flash only allows bits to be flipped from 1's to 0's on write */
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oldval = ldl_le_p(s->storage + offset);
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oldval &= value;
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stl_le_p(s->storage + offset, oldval);
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memory_region_flush_rom_device(&s->flash, offset, size);
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} else {
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qemu_log_mask(LOG_GUEST_ERROR,
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"%s: Flash write 0x%" HWADDR_PRIx" while flash not writable.\n",
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__func__, offset);
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}
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}
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static const MemoryRegionOps flash_ops = {
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.write = flash_write,
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.valid.min_access_size = 4,
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.valid.max_access_size = 4,
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.endianness = DEVICE_LITTLE_ENDIAN,
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};
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static void nrf51_nvm_init(Object *obj)
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{
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NRF51NVMState *s = NRF51_NVM(obj);
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SysBusDevice *sbd = SYS_BUS_DEVICE(obj);
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memory_region_init_io(&s->mmio, obj, &io_ops, s, "nrf51_soc.nvmc",
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NRF51_NVMC_SIZE);
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sysbus_init_mmio(sbd, &s->mmio);
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memory_region_init_io(&s->ficr, obj, &ficr_ops, s, "nrf51_soc.ficr",
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sizeof(ficr_content));
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sysbus_init_mmio(sbd, &s->ficr);
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memory_region_init_io(&s->uicr, obj, &uicr_ops, s, "nrf51_soc.uicr",
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sizeof(s->uicr_content));
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sysbus_init_mmio(sbd, &s->uicr);
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}
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static void nrf51_nvm_realize(DeviceState *dev, Error **errp)
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{
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NRF51NVMState *s = NRF51_NVM(dev);
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Error *err = NULL;
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memory_region_init_rom_device(&s->flash, OBJECT(dev), &flash_ops, s,
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"nrf51_soc.flash", s->flash_size, &err);
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if (err) {
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error_propagate(errp, err);
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return;
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}
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s->storage = memory_region_get_ram_ptr(&s->flash);
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sysbus_init_mmio(SYS_BUS_DEVICE(dev), &s->flash);
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}
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static void nrf51_nvm_reset(DeviceState *dev)
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{
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NRF51NVMState *s = NRF51_NVM(dev);
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s->config = 0x00;
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memset(s->uicr_content, 0xFF, sizeof(s->uicr_content));
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}
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static Property nrf51_nvm_properties[] = {
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DEFINE_PROP_UINT32("flash-size", NRF51NVMState, flash_size, 0x40000),
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DEFINE_PROP_END_OF_LIST(),
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};
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static const VMStateDescription vmstate_nvm = {
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.name = "nrf51_soc.nvm",
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.version_id = 1,
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.minimum_version_id = 1,
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.fields = (VMStateField[]) {
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VMSTATE_UINT32_ARRAY(uicr_content, NRF51NVMState,
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NRF51_UICR_FIXTURE_SIZE),
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VMSTATE_UINT32(config, NRF51NVMState),
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VMSTATE_END_OF_LIST()
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}
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};
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static void nrf51_nvm_class_init(ObjectClass *klass, void *data)
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{
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DeviceClass *dc = DEVICE_CLASS(klass);
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dc->props = nrf51_nvm_properties;
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dc->vmsd = &vmstate_nvm;
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dc->realize = nrf51_nvm_realize;
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dc->reset = nrf51_nvm_reset;
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}
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static const TypeInfo nrf51_nvm_info = {
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.name = TYPE_NRF51_NVM,
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.parent = TYPE_SYS_BUS_DEVICE,
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.instance_size = sizeof(NRF51NVMState),
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.instance_init = nrf51_nvm_init,
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.class_init = nrf51_nvm_class_init
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};
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static void nrf51_nvm_register_types(void)
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{
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type_register_static(&nrf51_nvm_info);
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}
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type_init(nrf51_nvm_register_types)
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@ -0,0 +1,64 @@
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/*
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* Nordic Semiconductor nRF51 non-volatile memory
|
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*
|
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* It provides an interface to erase regions in flash memory.
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* Furthermore it provides the user and factory information registers.
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*
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* QEMU interface:
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* + sysbus MMIO regions 0: NVMC peripheral registers
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* + sysbus MMIO regions 1: FICR peripheral registers
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* + sysbus MMIO regions 2: UICR peripheral registers
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* + flash-size property: flash size in bytes.
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*
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* Accuracy of the peripheral model:
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* + Code regions (MPU configuration) are disregarded.
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*
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* Copyright 2018 Steffen Görtz <contrib@steffen-goertz.de>
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*
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* This code is licensed under the GPL version 2 or later. See
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* the COPYING file in the top-level directory.
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*
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*/
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#ifndef NRF51_NVM_H
|
||||
#define NRF51_NVM_H
|
||||
|
||||
#include "hw/sysbus.h"
|
||||
#define TYPE_NRF51_NVM "nrf51_soc.nvm"
|
||||
#define NRF51_NVM(obj) OBJECT_CHECK(NRF51NVMState, (obj), TYPE_NRF51_NVM)
|
||||
|
||||
#define NRF51_UICR_FIXTURE_SIZE 64
|
||||
|
||||
#define NRF51_NVMC_SIZE 0x1000
|
||||
|
||||
#define NRF51_NVMC_READY 0x400
|
||||
#define NRF51_NVMC_READY_READY 0x01
|
||||
#define NRF51_NVMC_CONFIG 0x504
|
||||
#define NRF51_NVMC_CONFIG_MASK 0x03
|
||||
#define NRF51_NVMC_CONFIG_WEN 0x01
|
||||
#define NRF51_NVMC_CONFIG_EEN 0x02
|
||||
#define NRF51_NVMC_ERASEPCR1 0x508
|
||||
#define NRF51_NVMC_ERASEPCR0 0x510
|
||||
#define NRF51_NVMC_ERASEALL 0x50C
|
||||
#define NRF51_NVMC_ERASEUICR 0x514
|
||||
#define NRF51_NVMC_ERASE 0x01
|
||||
|
||||
#define NRF51_UICR_SIZE 0x100
|
||||
|
||||
typedef struct NRF51NVMState {
|
||||
SysBusDevice parent_obj;
|
||||
|
||||
MemoryRegion mmio;
|
||||
MemoryRegion ficr;
|
||||
MemoryRegion uicr;
|
||||
MemoryRegion flash;
|
||||
|
||||
uint32_t uicr_content[NRF51_UICR_FIXTURE_SIZE];
|
||||
uint32_t flash_size;
|
||||
uint8_t *storage;
|
||||
|
||||
uint32_t config;
|
||||
|
||||
} NRF51NVMState;
|
||||
|
||||
|
||||
#endif
|
||||
Loading…
Reference in New Issue